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hc05 mc68hc05bd3d/h mc68hc05bd3 mc68hc705bd3 mc68hc05bd5 technical data !motorola mc68hc05bd3 !motorola technical data

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tpg 1 general description pin description and i/o ports memory and registers resets and interrupts multi-function timer pulse width modulation m-bus serial interface sync signal processor cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705bd3 mc68hc05bd5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 general description pin description and i/o ports memory and registers resets and interrupts multi-function timer pulse width modulation m-bus serial interface sync signal processor cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705bd3 mc68hc05bd5 tpg 2
all products are sold on motorola? terms & conditions of supply. in ordering a product covered by this document the customer agrees to be bound by those terms & conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this notice). a copy of motorola? terms & conditions of supply is available on request. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals? must be validated for each customer application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and ! are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. the customer should ensure that it has the most up to date version of the document by contacting its local motorola office. this document supersedes any earlier documentation relating to the products referred to herein. the information contained in this document is current at the date of publication. it may subsequently be updated, revised or withdrawn. motorola ltd., 1996 all trade marks recognized. this document contains information on new products. speci?ations and information herein are subject to change without notice. mc68hc05bd3 mc68hc705bd3 mc68hc05bd5 high-density complementary metal oxide semiconductor (hcmos) microcontroller unit tpg 3
tpg 4 conventions register and bit mnemonics are de?ed in the paragraphs describing them. an overbar is used to designate an active-low signal, eg: reset . unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; ? is used to indicate an unde?ed state (on reset).
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mc68hc05bd3 motorola i paragraph number page number title table of contents 1 general description 1.1 features.................................................................................................................1-1 2 pin description and i/o ports 2.1 pin descriptions.............................................................................................2-1 2.2 pin assignments ....................................................................................................2-2 2.3 input/output ports.......................................................................................2-3 2.3.1 port a ...............................................................................................................2-3 2.3.2 port b ...............................................................................................................2-3 2.3.3 port c ...............................................................................................................2-4 2.3.4 port d ...............................................................................................................2-4 2.3.5 input/output programming...............................................................................2-4 2.3.6 port c and d con?uration registers..............................................................2-5 3 memory and registers 3.1 registers ...............................................................................................................3-1 3.2 ram (mc68hc05bd3)..........................................................................................3-1 3.3 ram (mc68hc705bd3/mc68hc05bd5).............................................................3-1 3.4 rom (mc68hc05bd3) .........................................................................................3-2 3.5 rom (mc68hc05bd5) .........................................................................................3-2 3.6 eprom (mc68hc705bd3) ..................................................................................3-2 3.7 bootstrap rom ......................................................................................................3-2 tpg 7
motorola ii mc68hc05bd3 paragraph number page number title 4 resets and interrupts 4.1 resets ................................................................................................................4-1 4.1.1 power-on reset (por) ...................................................................................4-1 4.1.2 reset pin.......................................................................................................4-1 4.1.3 illegal address (iladr) reset.........................................................................4-2 4.1.4 computer operating properly (cop) reset ....................................................4-2 4.2 interrupts........................................................................................................4-3 4.2.1 non-maskable software interrupt (swi) ..........................................................4-3 4.2.2 maskable hardware interrupts.........................................................................4-5 4.2.2.1 external interrupt (irq )..............................................................................4-5 4.2.2.2 sync signal processor interrupt.................................................................4-7 4.2.2.3 m-bus interrupts.........................................................................................4-7 4.2.2.4 multi-function timer interrupts ..................................................................4-8 5 multi-function timer 5.1 mft counter register ...........................................................................................5-1 5.2 mft control and status register ..........................................................................5-1 5.3 cop watchdog......................................................................................................5-2 6 pulse width modulation 6.1 pwm registers .....................................................................................................6-1 6.2 general operation .................................................................................................6-1 7 m-bus serial interface 7.1 m-bus interface features ......................................................................................7-1 7.2 m-bus protocol ......................................................................................................7-2 7.2.1 start signal...................................................................................................7-3 7.2.2 slave address transmission ............................................................................7-3 7.2.3 data transfer....................................................................................................7-4 7.2.4 repeated start signal ..................................................................................7-4 7.2.5 stop signal ....................................................................................................7-4 7.2.6 arbitration procedure .......................................................................................7-4 7.2.7 clock synchronization .....................................................................................7-5 7.2.8 handshaking....................................................................................................7-5 7.3 m-bus registers ....................................................................................................7-5 tpg 8
mc68hc05bd3 motorola iii paragraph number page number title 7.3.1 m-bus address register (madr) ....................................................................7-6 7.3.2 m-bus frequency register (mfdr).................................................................7-6 7.3.3 m-bus control register (mcr) ........................................................................7-7 7.3.4 m-bus status register (msr)..........................................................................7-8 7.3.5 m-bus data i/o register (mdr) ......................................................................7-9 7.4 programming considerations ................................................................................7-11 7.4.1 initialization ......................................................................................................7-11 7.4.2 generation of a start signal and the first byte of data transfer..................7-11 7.4.3 software responses after transmission or reception of a byte .....................7-11 7.4.4 generation of the stop signal........................................................................7-12 7.4.5 generation of a repeated start signal ........................................................7-13 7.4.6 slave mode ......................................................................................................7-13 7.4.7 arbitration lost .................................................................................................7-13 8 sync signal processor 8.1 functional blocks...................................................................................................8-1 8.1.1 polarity correction............................................................................................8-1 8.1.1.1 separate vertical sync input ......................................................................8-2 8.1.1.2 separate horizontal or composite sync input ..........................................8-3 8.1.2 sync detection.................................................................................................8-3 8.1.3 free-running pseudo sync signal generator ..................................................8-4 8.1.4 sync separation...............................................................................................8-4 8.1.5 vertical sync pulse reshaper..........................................................................8-5 8.1.6 sync signal counters ......................................................................................8-5 8.2 vsync interrupt....................................................................................................8-5 8.3 registers ...............................................................................................................8-7 8.3.1 sync signal control & status register (sscsr).............................................8-7 8.3.2 vertical frequency registers (vfrs) ..............................................................8-9 8.3.3 line frequency registers (lfrs) ....................................................................8-9 8.3.4 sync signal control register (sscr)..............................................................8-10 8.3.5 horizontal sync period width register (hpwr)..............................................8-10 8.4 system operation ..................................................................................................8-11 9 cpu core and instruction set 9.1 registers ...............................................................................................................9-1 9.1.1 accumulator (a) ...............................................................................................9-1 9.1.2 index register (x)..............................................................................................9-2 9.1.3 program counter (pc) ......................................................................................9-2 9.1.4 stack pointer (sp) ............................................................................................9-2 9.1.5 condition code register (ccr).........................................................................9-2 tpg 9
motorola iv mc68hc05bd3 paragraph number page number title 9.2 instruction set ........................................................................................................9-3 9.2.1 register/memory instructions ..........................................................................9-4 9.2.2 branch instructions ..........................................................................................9-4 9.2.3 bit manipulation instructions ............................................................................9-4 9.2.4 read/modify/write instructions.........................................................................9-4 9.2.5 control instructions ..........................................................................................9-4 9.2.6 tables...............................................................................................................9-4 9.3 addressing modes.................................................................................................9-11 9.3.1 inherent............................................................................................................9-11 9.3.2 immediate ........................................................................................................9-11 9.3.3 direct ...............................................................................................................9-11 9.3.4 extended..........................................................................................................9-12 9.3.5 indexed, no offset ............................................................................................9-12 9.3.6 indexed, 8-bit offset .........................................................................................9-12 9.3.7 indexed, 16-bit offset .......................................................................................9-12 9.3.8 relative ............................................................................................................9-13 9.3.9 bit set/clear ......................................................................................................9-13 9.3.10 bit test and branch...........................................................................................9-13 10 low power modes 10.1 stop mode.........................................................................................................10-1 10.2 wait mode..........................................................................................................10-1 10.3 cop watchdog timer considerations.................................................................10-2 11 operating modes 11.1 user mode (normal operation) ...........................................................................11-2 11.2 self-check mode .................................................................................................11-2 11.3 bootstrap mode ...................................................................................................11-4 12 electrical specifications 12.1 maximum ratings................................................................................................12-1 12.2 thermal characteristics ......................................................................................12-1 12.3 dc electrical characteristics...............................................................................12-2 12.4 control timing .....................................................................................................12-3 12.5 m-bus timing ......................................................................................................12-4 12.6 sync signal processor timing.............................................................................12-5 tpg 10
mc68hc05bd3 motorola v paragraph number page number title 13 mechanical specifications 13.1 42-pin sdip package (case 858-01) ..................................................................13-1 13.2 40-pin dip package (case 711-03).....................................................................13-1 14 mc68hc705bd3 14.1 features...............................................................................................................14-1 14.2 memory map........................................................................................................14-1 14.3 eprom programming .........................................................................................14-1 14.3.1 programming control register (pcr)............................................................14-3 14.3.2 eprom programming sequence ..................................................................14-3 14.4 dc electrical characteristics ...............................................................................14-4 15 mc68hc05bd5 15.1 features...............................................................................................................15-1 15.2 memory map........................................................................................................15-1 15.3 dc electrical characteristics ...............................................................................15-3 tpg 11
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mc68hc05bd3 motorola vii figure number page number title list of figures 1-1 mc68hc05bd3/mc68hc705bd3/mc68hc05bd5 block diagram ......................1-2 2-1 pin assignment for 40-pin dip package.................................................................2-2 2-2 pin assignment for 42-pin sdip package ..............................................................2-3 2-3 parallel port i/o circuitry ........................................................................................2-6 3-1 memory map ..........................................................................................................3-3 4-1 power-on reset and reset timing......................................................................4-2 4-2 interrupt stacking order .........................................................................................4-4 4-3 external interrupt circuit and timing ......................................................................4-6 6-1 8-bit pwm output waveforms................................................................................6-2 7-1 m-bus interface block diagram ..............................................................................7-2 7-2 m-bus transmission signal diagram ......................................................................7-3 7-3 clock synchronization ............................................................................................7-5 7-4 flowchart of m-bus interrupt routine.....................................................................7-10 8-1 sync signal processor block diagram ...................................................................8-2 8-2 sync signal polarity correction ..............................................................................8-3 8-3 sync separator.......................................................................................................8-4 8-4 sync signal counters block diagram.....................................................................8-6 8-5 vertical frequency counter timing ........................................................................8-6 8-6 typical monitor system operation..........................................................................8-12 9-1 programming model ...............................................................................................9-1 9-2 stacking order ........................................................................................................9-2 10-1 wait flowchart ....................................................................................................10-2 11-1 flowchart of mode entering .................................................................................11-1 11-2 self-check mode timing ......................................................................................11-2 11-3 mc68hc05bd3 self-test circuit..........................................................................11-3 12-1 m-bus timing........................................................................................................12-4 14-1 mc68hc705bd3 memory map............................................................................14-2 15-1 mc68hc05bd5 memory map..............................................................................15-2 tpg \13
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mc68hc05bd3 motorola ix ta b l e number page number title list of tables 2-1 i/o pin functions ....................................................................................................2-4 2-2 con?uration for pc6 and pc7 ..............................................................................2-5 3-1 register outline......................................................................................................3-4 4-1 reset/interrupt vector addresses ..........................................................................4-4 5-1 cop reset and rti rates .....................................................................................5-3 7-1 m-bus prescaler .....................................................................................................7-6 8-1 vertical frame frequencies ....................................................................................8-9 9-1 mul instruction.......................................................................................................9-5 9-2 register/memory instructions.................................................................................9-5 9-3 branch instructions .................................................................................................9-6 9-4 bit manipulation instructions...................................................................................9-6 9-5 read/modify/write instructions ...............................................................................9-7 9-6 control instructions.................................................................................................9-7 9-7 instruction set .........................................................................................................9-8 9-8 m68hc05 opcode map...........................................................................................9-10 11-1 mode selection.....................................................................................................11-2 11-2 self-check report ................................................................................................11-4 12-1 dc electrical characteristics for mc68hc05bd3 ................................................12-2 12-2 control timing ......................................................................................................12-3 12-3 m-bus interface input signal timing.....................................................................12-4 12-4 m-bus interface output signal timing..................................................................12-4 12-5 sync signal processor timing..............................................................................12-5 14-1 mc68hc705bd3 programming boards...............................................................14-1 14-2 dc electrical characteristics for mc68hc705bd3 ..............................................14-4 15-1 dc electrical characteristics for mc68hc05bd5 ................................................15-3 tpg 15
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mc68hc05bd3 motorola 1-1 general description 1 1 general description the mc68hc05bd3 hcmos microcontroller is a member of the m68hc05 family of low-cost single-chip microcontrollers. this 8-bit microcontroller unit (mcu) contains an on-chip oscillator, cpu, ram, rom, parallel i/o capability with pins programmable as input or output, m-bus serial interface system (i 2 c), pulse width modulator, multi-function timer, and sync signal processor. these features make it particularly suitable as a multi-sync computer monitor mcu. the mc68hc05bd5 is functionally equivalent to mc68hc05bd3, with increase ram and rom. the mc68hc705bd3 is an eprom version of the mc68hc05bd5. all references to the mc68hc05bd3 apply equally to the mc68hc705bd3 and mc68hc05bd5, unless otherwise stated. references speci? to the mc68hc705bd3 are italicized in the text and also, for quick reference, they are summarized in section 14. references to mc68hc05bd5 are summarized in section 15. 1.1 features fully static chip design featuring the industry standard 8-bit m68hc05 core power saving wait mode 128 bytes of on-chip ram for mc68hc05bd3 256 bytes for mc68hc705bd3 and mc68hc05bd5 3.75k-bytes of user rom for mc68hc05bd3 7.75k-bytes of user rom for mc68hc05bd5 7.75k-bytes of user eprom for mc68hc705bd3 24 bidirectional i/o lines: 14 dedicated and 10 multiplexed i/o lines. 4 of the 14 dedicated i/o lines and 6 of the muxed i/o lines have +10v open-drain o/ps. 16 channels pwm outputs: 8 dedicated, +10v open-drain pwm channels and 8 multiplexed with i/o lines of which 6 of them have +10v open-drain outputs. m-bus serial interface (i 2 c-bus ? ) multi-function timer (mft) with periodic interrupt cop watchdog reset tpg 17 ? i 2 c-bus is a proprietary philips interface bus
motorola 1-2 mc68hc05bd3 general description 1 horizontal and vertical sync signal processor self-check mode available in 40-pin dip and 42-pin sdip packages figure 1-1 mc68hc05bd3/mc68hc705bd3/mc68hc05bd5 block diagram user rom self-check rom - 224 bytes 128 bytes for mc68hc05bd3 accumulator index register stack pointer program counter condition code register m68hc05 cpu reset irq/ vpp 0 12 1 1h i nzc osc power extal xtal vdd vss ddr a port a pa0 - pa7 pc0/pwm8* pc1/pwm9* pc2/pwm10* pc3/pwm11* pc4/pwm12* pc5/pwm13* pc6/pwm14/vttl pc7/pwm15/httl 8 ? 2 pwm 1 1 7 0 7 50 1 0 0 0 0 0 0 4 15 0 7 ddr b port b pb2* - pb5* ddr c port c pd0/sda? pd1/scl? m-bus ddr d port d 4 pwm0* pwm1* pwm2* pwm3* pwm4* pwm5* pwm6* pwm7* sync vsync hsync signal processor (ssp) mft (with cop) reset 3.75k-bytes for mc68hc05bd3 7.75k-bytes for mc68hc05bd5 7.75k-bytes eprom for mc68hc705bd3 bootstrap rom - 480 bytes for mc68hc705bd3 only for mc68hc05bd3 & mc68hc05bd5 only * +10v open-drain ? +5v open-drain if the pin is con?ured as sda or scl 256 bytes for mc68hc705bd3 & mc68hc05bd5 ram pb0 pb1 0 0 tpg 18
mc68hc05bd3 motorola 2-1 pin description and i/o ports 2 2 pin description and i/o ports this section provides a description of the functional pins and i/o programming of the mc68hc05bd3 microcontroller. 2.1 pin descriptions pin name 40-pin dip pin no. 42-pin sdip pin no. description vdd, vss 5, 6 5, 7 power is supplied to the mcu using these two pins. vdd is power and vss is ground. irq / vpp 15 16 in the user mode this pin an external hardware interrupt irq . it is software programmable to provide two choices of interrupt triggering sensitivity. these options are: 1) negative edge-sensitive triggering only, or 2) both negative edge-sensitive and level sensitive triggering. in the bootstrap mode on the mc68hc705bd3, this is the eprom programming voltage input pin. reset 44 the active low reset input is not required for start-up, but can be used to reset the mcu internal state and provide an orderly software start-up procedure. xtal, extal 7, 8 8, 9 these pins provide connections to the on-chip oscillator. the oscillator can be driven by a at-crystal circuit or a ceramic resonator with a frequency of 4.2 mhz. extal may also be driven by an external oscillator if an external crystal/resonator circuit is not used. see figure 11-3 for values of crystal circuit external components. pa0-pa7 23-16 24-17 these eight i/o lines comprise port a. the state of any pin is software programmable. all port a lines are con?ured as input during power on or external reset. pb0-pb5 14-9 15-10 these six i/o lines comprise port b. the state of any pin is software programmable. all port b lines are con?ured as input during power on or external reset. pb2 to pb5 are +10v open-drain pins. pc0/pwm8 to pc5/pwm13 26-31 27-32 these six port c pins are +10v open-drain type. the state of any pin is software programmable. all port c lines are con?ured as input during power on or external reset. these pins become pwm output channels 8 to 13 by setting the appropriate bits in con?uration register 1 ($0a). tpg 19
motorola 2-2 mc68hc05bd3 pin description and i/o ports 2 2.2 pin assignments pc6/pwm14/vttl, pc7/pwm15/httl 32, 33 33, 34 these two port c i/o lines are shared with the pwm and sync signal processor. con?uration for use are set by the con?uration register 1 ($0a) and con?uration register 2 ($0b). pd0/sda, pd1/scl 24, 25 25, 26 these two port d i/o lines are shared with the m-bus lines sda and scl. when con?ured as m-bus lines in con?uration register 2 ($0b), these pins become +5v open-drain pins. pwm0 to pwm7 3-1, 38-34 3-1, 40-38, 36, 35 these eight pins are dedicated for the 8-bit pwm channel 0 to 7. hsync, vsync 39, 40 41, 42 these two pins are for video sync signals input from the host computer. the polarity of the input signals can either be positive or negative. these two pins contain internal schmitt triggers as part of their inputs to improve noise immunity figure 2-1 pin assignment for 40-pin dip package pin name 40-pin dip pin no. 42-pin sdip pin no. description 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pwm2 pwm1 pwm0 reset vdd vss xtal extal pb5 pb4 pb3 pb2 pb1 pb0 irq / vpp pa7 pa6 pa5 pa4 pa3 vsync hsync pwm3 pwm4 pwm5 pwm6 pwm7 pc7/pwm15/httl pc6/pwm14/vttl pc5/pwm13 pc4/pwm12 pc3/pwm11 pc2/pwm10 pc1/pwm9 pc0/pwm8 pd1/scl pd0/sda pa0 pa1 pa2 tpg 20
mc68hc05bd3 motorola 2-3 pin description and i/o ports 2 2.3 input/output ports in the user mode there are 24 bidirectional i/o lines arranged as 4 i/o ports (port a, b, c, and d). the individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (ddrs). also, if enabled by software, port c and d will have additional functions as pwm outputs, m-bus i/o and sync signal processor outputs. 2.3.1 port a port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $00 and the data direction register (ddr) is at $04. reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 2.3.2 port b port b is a 6-bit bidirectional port which does not share any of its pins with other subsystems. pb2 to pb5 are +10v open-drain port pins. the port b data register is at $01 and the data direction register (ddr) is at $05. reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. figure 2-2 pin assignment for 42-pin sdip package 42 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 pwm2 pwm1 pwm0 reset vdd nc vss xtal extal pb5 pb4 pb3 pb2 pb1 pb0 irq / vpp pa7 pa6 pa5 pa4 pa3 vsync hsync pwm3 pwm4 pwm5 nc pwm6 pwm7 pc7/pwm15/httl pc6/pwm14/vttl pc5/pwm13 pc4/pwm12 pc3/pwm11 pc2/pwm10 pc1/pwm9 pc0/pwm8 pd1/scl pd0/sda pa0 pa1 pa2 tpg 21
motorola 2-4 mc68hc05bd3 pin description and i/o ports 2 2.3.3 port c port c is an 8-bit bidirectional port which shares pins with pwm and ssp subsystem. see section 6 for a detailed description of pwm and section 8 for a detailed description of ssp. these pins are con?ured to pwm output when the corresponding bits in the con?uration register 1 are set, except pc6 and pc7. pc6 and pc7 are con?ured to ssp outputs when the corresponding bits in the con?uration register 2 are set. the port c data register is at $02 and the data direction register (ddr) is at $06. reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 2.3.4 port d port d is a 2-bit bidirectional port which shares pins with m-bus subsystem. see section 7 for a detailed description of m-bus. these pins are con?ured to the corresponding functions when the corresponding bits in the con?uration register 2 are set. they are +5v open-drain i/o pins when used as m-bus i/o. the port d data register is at $03 and the data direction register (ddr) is at $07. reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 2.3.5 input/output programming bidirectional port lines may be programmed as an input or an output under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each port has an associated ddr. any i/o port pin is con?ured as an output if its corresponding ddr bit is set. a pin is con?ured as an input if its corresponding ddr bit is cleared. during reset, all ddrs are cleared, which con?ure all port pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. table 2-1 i/o pin functions r/w ddr i/o pin function 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read. tpg 22
mc68hc05bd3 motorola 2-5 pin description and i/o ports 2 2.3.6 port c and d con?uration registers port c and port d are shared with pwm, m-bus and ssp. the con?uration registers at $0a and $0b are used to con?ure those i/o pins. they are default to zero after power-on reset. setting these bits will set the corresponding pins to the corresponding functions, except pc6 and pc7. for example, setting scl and sda bits of register $0b will con?ure port d pins 1 and 0 as m-bus pins, regardless of ddr1 and ddr0 settings. pc7 and pc6 are shared with both pwm and ssp. when httl and vttl in $000b are set, pc7 and pc6 are con?ured as httl and vttl outputs respectively, regardless of the status of pwm15 and pwm14 in $000a. that is, httl and vttl settings override pwm15 and pwm14 settings. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset con?uration register 1 $000a pwm15 pwm14 pwm13 pwm12 pwm11 pwm10 pwm9 pwm8 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset con?uration register 2 $000b httl vttl scl sda 0000 0000 table 2-2 con?uration for pc6 and pc7 pwm15 httl result of pc7 pwm14 vttl result of pc6 0 0 pc7 0 0 pc6 0 1 httl 0 1 vttl 1 0 pwm15 1 0 pwm14 1 1 httl 1 1 vttl tpg 23
motorola 2-6 mc68hc05bd3 pin description and i/o ports 2 figure 2-3 parallel port i/o circuitry input register bit input i/o output i/o pin data direction register bit latched output data bit internal mc68hc05 connections ddr 7 ddr 6 ddr 5 ddr 4 ddr 3 ddr 2 ddr 1 ddr 0 0 1 2 3 4 5 6 7 px7 px6 px5 px4 px3 px2 px1 px0 typical port data direction register typical port register i/o port lines & + v dd pad ip port data port ddr internal logic p n note: (1) ip = input protection (2) latch-up protection not shown (a) (b) (c) tpg 24
mc68hc05bd3 motorola 3-1 memory and registers 3 3 memory and registers the mc68hc05bd3/mc68hc705bd3/mc68hc05bd5 has a 16k-byte memory map consisting of registers, user rom/ eprom , user ram, self-check/ bootstrap rom, and i/o as shown in figure 3-1. 3.1 registers all the i/o, control and status registers of the mc68hc05bd3 are contained within the ?st 48-byte block of the memory map (address $0000 to $002f). 3.2 ram (mc68hc05bd3) the user ram consists of 128 bytes of memory, from $0080 to $00ff. this is shared with a 64 byte stack area. the stack begins at $00ff and counts down to $00c0. 3.3 ram (mc68hc705bd3/mc68hc05bd5) the user ram consists of 256 bytes of memory, from $0080 to $017f. this is shared with a 64 byte stack area. the stack begins at $00ff and counts down to $00c0. note: using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call. tpg 25
motorola 3-2 mc68hc05bd3 memory and registers 3 3.4 rom (mc68hc05bd3) the user rom consists of 3.75k-bytes of memory, from $3000 to $3eff. 3.5 rom (mc68hc05bd5) the user rom consists of 7.75k-bytes of memory, from $2000 to $3eff. 3.6 eprom (mc68hc705bd3) the user eprom consists of 7.75k-bytes of memory, from $2000 to $3eff. 3.7 bootstrap rom this is available on the mc68hc705bd3 device only. it stores the on-chip program for programming the user eprom. tpg 26
mc68hc05bd3 motorola 3-3 memory and registers 3 figure 3-1 memory map unused port a data register $00 $0000 i/o 48 bytes self-check 16 bytes user vectors 16 bytes vectors port b data register $01 port c data register $02 port d data register $03 port a data direction register $04 port b data direction register $05 port c data direction register $06 port d data direction register $07 mft control and status register $08 mft timer counter register $09 con?uration register 1 $0a con?uration register 2 $0b $0c $0d $0e $0f $10 $11 unused $12 unused $13 unused $14 unused $15 unused $16 mbus address register $17 mbus frequency divider register $18 mbus control register $19 mbus status register $1a mbus data register $1b $1c programming control register $1d hsync period width register $1e reserved $1f ssp control and status register vertical frequency high register vertical frequency low register line frequency high register line frequency low register sync signal control register unused unused user rom 3840 bytes $002f $0080 $0100 $2fff $3000 $3f00 $3fdf $3fe0 $3fef $3ff0 $3fff $3eff mc68hc05bd3 reserved $3ff0 reserved $3ff2 mft $3ff4 mbus $3ff6 ssp $3ff8 irq $3ffa swi $3ffc reset $3ffe $20 $21 pwm2 $22 pwm3 $23 pwm4 $24 pwm5 $25 pwm6 $26 pwm7 $27 pwm8 $28 pwm9 $29 pwm10 $2a pwm11 $2b pwm12 $2c pwm13 $2d pwm14 $2e pwm15 $2f pwm0 pwm1 $00ff $00c0 $0030 $007f self-check 224 bytes program $0000 i/o 48 bytes self-check 16 bytes user vectors 16 bytes vectors unused user ram 256 bytes unused user rom 7936 bytes stack 64 bytes $002f $0080 $0180 $1fff $2000 $3f00 $3fdf $3fe0 $3fef $3ff0 $3fff $3eff mc68hc05bd5 $00ff $00c0 $0030 $007f $017f unused $0000 i/o 48 bytes bootstrap 16 bytes user vectors 16 bytes vectors unused user ram 256 bytes unused user eprom 7936 bytes stack 64 bytes $002f $0080 $0180 $1fff $2000 $3f00 $3fdf $3fe0 $3fef $3ff0 $3fff $3eff mc68hc705bd3 $00ff $00c0 $0030 $007f $017f bootstrap rom 480 bytes unused $1fe0 $1fdf $1e00 $1dff self-check 224 bytes program user ram 128 bytes stack 64 bytes tpg 27
motorola 3-4 mc68hc05bd3 memory and registers 3 table 3-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 unde?ed port b data $0001 pb5 pb4 pb3 pb2 pb1 pb0 unde?ed port c data $0002 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 unde?ed port d data $0003 pd1 pd0 unde?ed port a data direction $0004 ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 0000 0000 port b data direction $0005 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 --00 0000 port c data direction $0006 ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 0000 0000 port d data direction $0007 ddrd1 ddrd0 ---- --00 mft control and status $0008 tof rtif tofie rtie irqn rt1 rt0 0000 0-11 mft timer counter $0009 mftcr7 mftcr6 mftcr5 mftcr4 mftcr3 mftcr2 mftcr1 mftcr0 0000 0000 con?uration 1 $000a pwm15 pwm14 pwm13 pwm12 pwm11 pwm10 pwm9 pwm8 0000 0000 con?uration 2 $000b httl vttl scl sda 00-- --00 ssp control and status $000c vpol hpol vdet hdet sout insrtb fout vsin 0000 0000 vertical frequency high $000d 0 0 0 vf12 vf11 vf10 vf9 vf8 0000 0000 vertical frequency low $000e vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 0000 0000 line frequency high $000f hover 0 0 0 lf11 lf10 lf9 lf8 0000 0000 line frequency low $0010 lf7 lf6 lf5 lf4 lf3 lf2 lf1 lf0 0000 0000 sync signal control $0011 vsie 0000000 0000 0000 unused $0012 unused $0013 unused $0014 unused $0015 unused $0016 mbus address $0017 mad7 mad6 mad5 mad4 mad3 mad2 mad1 0000 000- mbus frequency divider $0018 fd4 fd3 fd2 fd1 fd0 ---0 0000 mbus control $0019 men mien msta mtx txak 0000 0--- mbus status $001a mcf mass mbb mal srw mif rxak 1000 -001 mbus data $001b md7 md6 md5 md4 md3 md2 md1 md0 unde?ed unused $001c programming control $001d elat pgm ---- --00 hsync period width $001e hpwr7 hpwr6 hpwr5 hpwr4 hpwr3 hpwr2 hpwr1 hpwr0 0000 0000 reserved $001f tpg 28
mc68hc05bd3 motorola 3-5 memory and registers 3 0pwm $0020 0pwm4 0pwm3 0pwm2 0pwm1 0pwm0 0brm2 0brm1 0brm0 0000 0000 1pwm $0021 1pwm4 1pwm3 1pwm2 1pwm1 1pwm0 1brm2 1brm1 1brm0 0000 0000 2pwm $0022 2pwm4 2pwm3 2pwm2 2pwm1 2pwm0 2brm2 2brm1 2brm0 0000 0000 3pwm $0023 3pwm4 3pwm3 3pwm2 3pwm1 3pwm0 3brm2 3brm1 3brm0 0000 0000 4pwm $0024 4pwm4 4pwm3 4pwm2 4pwm1 4pwm0 4brm2 4brm1 4brm0 0000 0000 5pwm $0025 5pwm4 5pwm3 5pwm2 5pwm1 5pwm0 5brm2 5brm1 5brm0 0000 0000 6pwm $0026 6pwm4 6pwm3 6pwm2 6pwm1 6pwm0 6brm2 6brm1 6brm0 0000 0000 7pwm $0027 7pwm4 7pwm3 7pwm2 7pwm1 7pwm0 7brm2 7brm1 7brm0 0000 0000 8pwm $0028 8pwm4 8pwm3 8pwm2 8pwm1 8pwm0 8brm2 8brm1 8brm0 0000 0000 9pwm $0029 9pwm4 9pwm3 9pwm2 9pwm1 9pwm0 9brm2 9brm1 9brm0 0000 0000 10pwm $002a 10pwm4 10pwm3 10pwm2 10pwm1 10pwm0 10brm2 10brm1 10brm0 0000 0000 11pwm $002b 11pwm4 11pwm3 11pwm2 11pwm1 11pwm0 11brm2 11brm1 11brm0 0000 0000 12pwm $002c 12pwm4 12pwm3 12pwm2 12pwm1 12pwm0 12brm2 12brm1 12brm0 0000 0000 13pwm $002d 13pwm4 13pwm3 13pwm2 13pwm1 13pwm0 13brm2 13brm1 13brm0 0000 0000 14pwm $002e 14pwm4 14pwm3 14pwm2 14pwm1 14pwm0 14brm2 14brm1 14brm0 0000 0000 15pwm $002f 15pwm4 15pwm3 15pwm2 15pwm1 15pwm0 15brm2 15brm1 15brm0 0000 0000 table 3-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset tpg 29
motorola 3-6 mc68hc05bd3 memory and registers 3 this page left blank intentionally tpg 30
mc68hc05bd3 motorola 4-1 resets and interrupts 4 4 resets and interrupts 4.1 resets the mc68hc05bd3 can be reset in four ways: by the initial power-on reset function, by an active low input to the reset pin, by an opcode fetch from an illegal address, and by a cop watchdog timer reset. any of these resets will cause the program to go to its starting address, speci?d by the contents of memory locations $3ffe and $3fff, and cause the interrupt mask of the condition code register to be set. 4.1.1 power-on reset (por) the power-on reset occurs when a positive transition is detected on the supply voltage, v dd . the power-on reset is used strictly for power-up conditions, and should not be used to detect any drops in the power supply voltage. there is no provision for a power-down reset. the power-on circuitry provides for a 4064 tcyc delay from the time that the oscillator becomes active. if the external reset pin is low at the end of the 4064 tcyc time out, the processor remains in the reset condition until reset goes high. the user must ensure that v dd has risen to a point where the mcu can operate properly prior to the time the 4064 por cycles have elapsed. if there is doubt, the external reset pin should remain low until such time that v dd has risen to the minimum operating voltage speci?d. 4.1.2 reset pin the reset input pin is used to reset the mcu to provide an orderly software start-up procedure. when using the external reset, the reset pin must stay low for a minimum of 1.5tcyc. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. tpg 31
motorola 4-2 mc68hc05bd3 resets and interrupts 4 4.1.3 illegal address (iladr) reset the mcu monitors all opcode fetches. if an illegal address space is accessed during an opcode fetch, an internal reset is generated. illegal address spaces consist of all unused locations within the memory map and the i/o registers (see figure 3-1). because the internal reset signal is used, the mcu comes out of an iladr reset in the same operating mode it was in when the opcode was fetched. 4.1.4 computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a speci? amount of time by a program reset sequence. figure 4-1 power-on reset and reset timing vdd xtal pin 1 internal clock 2 internal address bus 2 internal data bus 2 reset 3ffe 3fff new pc 3ffe 3ffe 3fff t vddr vdd threshold (typically 1-2v) 4064 t cyc t oxov t cyc 3 new pch new pcl op code t rl =1.5t cyc pch pcl op code new pc notes: 1. xtal is not meant to represent frequency. it is only used to represent time. 2. internal clock, internal address bus, and internal data bus signals are not available externally. 3. next rising edge of internal clock after rising edge of reset initiates reset sequence. tpg 32
mc68hc05bd3 motorola 4-3 resets and interrupts 4 note: cop time-out is prevented by periodically writing a ? to bit 0 of address $3ff0. if the watchdog timer is allowed to time-out, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu comes out of a cop reset in the same operating mode it was in when the cop time-out was generated. the cop reset function is always enabled. see section 5.3 for more information on the cop watchdog timer. 4.2 interrupts the mcu can be interrupted by different sources ?four maskable hardware interrupt and one non-maskable software interrupt: external signal on the irq pin multi-function timer (mft) m-bus interface (mbus) sync signal processor (ssp) software interrupt instruction (swi) if the interrupt mask bit (i-bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i-bit enables interrupts. interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i-bit clear) the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. table 4-1 shows the relative priority of all the possible interrupt sources. 4.2.1 non-maskable software interrupt (swi) the software interrupt (swi) is an executable instruction and a non-maskable interrupt: it is execute regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupt enabled), swi is executed after interrupts that were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the swi interrupt service routine address is speci?d by the contents of memory locations $3ffc and $3ffd. tpg 33
motorola 4-4 mc68hc05bd3 resets and interrupts 4 figure 4-2 interrupt stacking order table 4-1 reset/interrupt vector addresses register flag name interrupt cpu interrupt vector address priority reset reset $3ffe-$3fff software swi $3ffc-$3ffd external interrupt irq $3ffa-$3ffb sscr vsync ssp $3ff8-$3ff9 msr mif m-bus mbus $3ff6-$3ff7 mftcsr tof timer over?w mft $3ff4-$3ff5 rtif real time interrupt $3ff2-$3ff3 $3ff0-$3ff1 condition code register accumulator index register program counter (high byte) program counter (low byte) $00c0 (bottom of stack) $00c1 $00c2 $00fd $00fe $00ff (top of stack) unstacking 1 2 3 4 5 5 4 3 2 1 stacking order order highest lowest tpg 34
mc68hc05bd3 motorola 4-5 resets and interrupts 4 4.2.2 maskable hardware interrupts if the interrupt mask bit (i-bit) of the ccr is set, all maskable interrupts (internal and external) are masked. clearing the i-bit allows interrupt processing to occur. note: the internal interrupt latch is cleared in the ?st part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i-bit is cleared. 4.2.2.1 external interrupt (irq ) the external interrupt irq can be software con?ured for ?egative-edge or ?egative-edge and level sensitive triggering by the irqn bit in the multi-function timer control and status register. irqn 1 (set) negative edge triggering for irq only 0 (clear) level and negative edge triggering for irq when the signal of the external interrupt pin, irq , satis?s the condition selected, an external interrupt occurs. the actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. when the interrupt is recognized, the current state of the processor is pushed onto the stack and the interrupt mask bit in the condition code register is set. this masks further interrupts until the present one is serviced. the service routine address is speci?d by the contents $3ffa & $3ffb. the interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) on the external interrupt line. figure 4-3 shows both a block diagram and timing for the interrupt line (irq ) to the processor. the ?st method is used if pulses on the interrupt line are spaced far enough apart to be serviced. the minimum time between pulses is equal to the number of cycles required to execute the interrupt service routine plus 21 cycles. once a pulse occurs, the next pulse should not occur until the mcu software has exited the routine (an rti occurs). the second con?uration shows several interrupt lines wired-or to perform the interrupt at the processor. thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized. note: the internal interrupt latch is cleared in the ?st part of the service routine; therefore, one (and only one) external interrupt pulse could be latched during t ilil and serviced as soon as the i bit is cleared. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mft control and status $0008 tof rtif tofie rtie irqn rt1 rt0 0000 0-11 tpg 35
motorola 4-6 mc68hc05bd3 resets and interrupts 4 figure 4-3 external interrupt circuit and timing + & external request interrupt power-on reset external reset external interrupt being serviced d c r q q v dd irq pin i bit (ccr) irq t ilih t ilil edge sensitive trigger condition the minimum pulse width t ilih is one internal bus period. the period t ilil should not be less than the number of t cyc cycles it takes to execute the interrupt service routine plus 21 tcyc cycles. t ilil wired ored interrupt signals irq if after servicing an interrupt the irq pin remains low, then the next interrupt is recognized. normally used with wired or connection. normally used with pull-up resistors for wired-or connection. (b) interrupt mode diagram (a) interrupt function diagram level sensitive trigger condition & + irqn bit (read of vectors) tpg 36
mc68hc05bd3 motorola 4-7 resets and interrupts 4 4.2.2.2 sync signal processor interrupt the vsync interrupt is generated by the sync signal processor (ssp) after a vertical sync pulse is detected as described in section 8. the interrupt enable bit, vsie, for the vsync interrupt is located at bit 7 of sync signal control register (sscr) at $0011. the i-bit in the ccr must be cleared in order for the vsync interrupt to be enabled. this interrupt will vector to the interrupt service routine located at the address speci?d by the contents of $3ff8 and $3ff9. the vsync interrupt latch will be cleared automatically by fetching of these vectors. refer to section 8 for detailed description of sync signal processor. 4.2.2.3 m-bus interrupts m-bus interrupt is enabled when the m-bus interrupt enable bit (mien) of m-bus control register is set, provided the interrupt mask bit of the condition code register is cleared. the interrupt service routine address is speci?d by the contents of memory location $3ff6 and $3ff7. mif - m-bus interrupt 1 (set) an m-bus interrupt has occurred. 0 (clear) an m-bus interrupt has not occurred. when this bit is set, an interrupt is generated to the cpu if mien is set. this bit is set when one of the following events occurs: 1) completion of one byte of data transfer. it is set at the falling edge of the 9th clock - mcf set. 2) a match of the calling address with its own speci? address in slave mode - maas set. 3) a loss of bus arbitration - mal set. this bit must be cleared by software in the interrupt routine. mcf - data transfer complete 1 (set) a byte transfer has been completed. 0 (clear) a byte is being transfer. maas - addressed as slave 1 (set) currently addressed as a slave. 0 (clear) not currently addressed. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset m-bus status register $001a mcf maas mbb mal srw mif rxak 1000 0001 tpg 37
motorola 4-8 mc68hc05bd3 resets and interrupts 4 then cpu needs to check the srw bit and set its mtx bit accordingly. writing to the m-bus control register clears this bit. mal - arbitration lost 1 (set) lost arbitration in master mode. 0 (clear) no arbitration lost. refer to section 7 for detailed description of m-bus interface. 4.2.2.4 multi-function timer interrupts there are two interrupt sources, tof and rtif bits of multi-function timer control and status register. the interrupt service routine address is speci?d by the contents of memory location $3ff4 and $3ff5. tof - timer over?w 1 (set) 8-bit ripple timer over?w has occurred. 0 (clear) no 8-bit ripple timer over?w has occurred. this bit is set when the 8-bit ripple counter over?ws from $ff to $00; a timer over?w interrupt will occur, if tofie is set. tof is cleared by writing a ? to the bit. rtif - real time interrupt flag 1 (set) a real time interrupt has occurred. 0 (clear) a real time interrupt has not occurred. the clock frequency that drives the rti circuit is e/16384, giving a maximum interrupt period of 8.19ms at a bus clock rate of 2mhz. a cpu interrupt request will be generated if rtie is set. rtif is cleared by writing a ? to the bit. refer to section 5 for detailed description of multi-function timer. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mft control and status register $0008 tof rtif tofie rtie irqn rt1 rt0 0000 0011 tpg 38
mc68hc05bd3 motorola 5-1 multi-function timer 5 5 multi-function timer the mft provides miscellaneous functions to the mc68hc05bd3 mcu. it includes a timer over?w function, real-time interrupt, and cop watchdog. the external interrupt (irq ) triggering option is also set by this modules mft control and status register. the clock base for this module is derived from the bus clock divided by four. for a 2mhz e (cpu) clock, the clock base is 0.5mhz. this clock base is then divided by an 8-stage ripple counter to generate the timer over?w. timer over?w rate is thus e/1024. the output of this 8-stage ripple counter then drives a 4-stage divider to generate real time interrupt. hence, the clock base for real time interrupt is e/16384. real time interrupt rate is selected by rt0 and rt1 bits of mft control and status register. the interrupt rates are e/16384, (e/16384)/2, (e/16384)/4, and (e/16384)/8. the selected real time interrupt rate is then divided by 8 to generate cop reset. 5.1 mft counter register the mft counter register (mftcr) can be read at location $0009. it is cleared by reset. 5.2 mft control and status register register bit de?itions: tof - timer over?w 1 (set) 8-bit ripple timer over?w has occurred. 0 (clear) no 8-bit ripple timer over?w has occurred. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mft control and status register $1c tof rtif tofie rtie irqn rt1 rt0 0000 0011 tpg 39
motorola 5-2 mc68hc05bd3 multi-function timer 5 this bit is set when the 8-bit ripple counter over?ws from $ff to $00; a timer over?w interrupt will occur, if tofie (bit 5) is set. tof is cleared by writing a ? to the bit. rtif - real time interrupt flag 1 (set) a real time interrupt has occurred. 0 (clear) a real time interrupt has not occurred. when rtif is set, a cpu interrupt request is generated if rite is set. the clock frequency that drives the rti circuit is e/16384 giving a maximum interrupt period of 8.19ms at a bus rate of 2mhz. rtif is cleared by writing a ? to the bit. tofie - timer over?w interrupt enable 1 (set) tof interrupt is enabled. 0 (clear) tof interrupt is disabled. rtie - real time interrupt enable 1 (set) real time interrupt is enabled. 0 (clear) real time interrupt is disabled. irqn - irq pin trigger option 1 (set) negative edge triggering for irq only 0 (clear) level and negative edge triggering for irq rt1, rt0 - rate select for cop watchdog and rti see section 5.3 on watchdog reset. 5.3 cop watchdog the cop (computer operating properly) watchdog timer function is implemented by using the output of the multi-function timer counter. the minimum cop reset rates are controlled by rt0 and rt1 of mft control and status register. if the cop circuit times out, an internal reset is generated and the reset vector is fetched (at $3ffe & $3fff). preventing a cop time-out is achieved by writing a ? to bit 0 of address $3ff0. the cop counter has to be cleared periodically by software with a period less than cop reset rate. the cop watchdog timer is always enabled and continues to count in wait mode. tpg 40
mc68hc05bd3 motorola 5-3 multi-function timer 5 table 5-1 cop reset and rti rates rt1 rt0 minimum cop reset period rti period cop e clock = 2mhz rti e clock = 2mhz 0 0 e/16384/7/1 57.344ms e/16384/1 8.192ms 0 1 e/16384/7/2 114.688ms e/16384/2 16.384ms 1 0 e/16384/7/4 229.376ms e/16384/4 32.768ms 1 1 e/16384/7/8 458.752ms e/16384/8 65.536ms note: rt0 and rt1 should only be changed immediately after cop watchdog timer has been reset. tpg 41
motorola 5-4 mc68hc05bd3 multi-function timer 5 this page left blank intentionally tpg 42
mc68hc05bd3 motorola 6-1 pulse width modulation 6 6 pulse width modulation the mc68hc05bd3 has 16 pwm channels. channel 0 to 7 are dedicated pwm channels. channel 8 to 15 are shared with port c i/o pins, and are selected by the respective bits in con?uration register 1. pwm channels 0 to 13 are +10v open-drain type; therefore a pull-up resistor is required at each of the pins. 6.1 pwm registers each pwm channel has an 8-bit register which contains a 5-bit pwm in the msb portion and a 3-bit binary rate multiplier (brm) in the lsb portion. the pwm channel data registers are located from $20 to $2f. 6.2 general operation the value programmed in the 5-bit pwm portion will determine the pulse length of the output. the clock to the 5-bit pwm portion is the e clock and the repetition rate of the output is hence 62.5khz at 2mhz e clock. the 3-bit brm will generate a number of narrow pulses which are equally distributed among an 8-pwm-cycle. the number of pulses generated is equal to the number programmed in the 3-bit brm portion. example of the waveforms are shown in figure 6-1. combining the 5-bit pwm together with the 3-bit brm, the average duty cycle at the output will be (m+n/8)/32, where m is the content of the 5-bit pwm portion, and n is the content of the 3-bit brm portion. using this mechanism, a true 8-bit resolution pwm is achieved. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset 0pwm $0020 0pwm4 0pwm3 0pwm2 0pwm1 0pwm0 0brm2 0brm1 0brm0 0000 0000 :: 15pwm $002f 15pwm4 15pwm3 15pwm2 15pwm1 15pwm0 15brm2 15brm1 15brm0 0000 0000 tpg 43
motorola 6-2 mc68hc05bd3 pulse width modulation 6 the value of each pwm data register is continuously compared with the content of an internal counter to determine the state of each pwm channel output pin. double buffering is not used in this pwm design. figure 6-1 8-bit pwm output waveforms m=$00 32t=16 m s m=$01 m=$0f m=$1f t=1 cpu clock period (0.5 m s if cpu cloc k=2mhz) pulse inserted at end of pwm cycle n pwm cycles where pulses are inserted in a 8-cycle frame number of inserted pulses in a 8-cycle frame xx1 4 1 x1x 2, 6 2 1xx 1, 3, 5, 7 4 31t 16t 16t 31t t m = value set in 5-bit pwm (bit3-bit7) n = value set in 3-bit brm (bit0-bit2) t depends on setting of n. tpg 44
mc68hc05bd3 motorola 7-1 m-bus serial interface 7 7 m-bus serial interface m-bus (motorola bus) is a two-wire, bidirectional serial bus which provides a simple, ef?ient way for data exchange between devices. it is fully compatible with the i 2 c bus standard. this two-wire bus minimizes the interconnection between devices and eliminates the need for address decoders; resulting in less pcb traces and economic hardware structure. this bus is suitable for applications requiring communications in a short distance among a number of devices. the maximum data rate is 100kbit/s. the maximum communication length and number of devices that can be connected are limited by a maximum bus capacitance of 400pf. the m-bus system is a true multi-master bus, including arbitration to prevent data collision if two or more masters intend to control the bus simultaneously. it may be used for rapid testing and alignment of end products via external connections to an assembly-line computer. 7.1 m-bus interface features compatible with i 2 c bus standard multi-master operation 32 software programmable serial clock frequencies software selectable acknowledge bit interrupt driven byte-by-byte data transfer arbitration lost driven interrupt with automatic mode switching from master to slave calling address identi?ation interrupt generate/detect the start, stop and acknowledge signals repeated start signal generation bus busy detection tpg 45
motorola 7-2 mc68hc05bd3 m-bus serial interface 7 7.2 m-bus protocol normally, a standard communication is composed of four parts, 1) start signal, 2) slave address transmission, 3) data transfer, and 4) stop signal. they are described brie? in the following sections and illustrated in figure 7-2. figure 7-1 m-bus interface block diagram internal bus frequency divider register address comparator address register 8 men mien msta mtx txak mcf maas mbb mal srw mif rxak tx shift register rx shift register rx control tx control m-bus interrupt scl control sda control m-bus clock generator sync logic start, stop detector and arbitration start, stop generator and timing sync scl sda control register status register interrupt tpg 46
mc68hc05bd3 motorola 7-3 m-bus serial interface 7 7.2.1 start signal when the bus is free, i.e., no master device is occupying the bus (both scl and sda lines are at logic high), a master may initiate communication by sending a start signal. as shown in figure 7-2, a start signal is de?ed as a high to low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves. 7.2.2 slave address transmission the ?st byte of data transfer immediately following the start signal is the slave address transmitted by the master. this is a seven bits long calling address followed by a r/w bit. the r/w bit dictates the slave of the desired direction of data transfer. only the slave with matched address will respond by sending back an acknowledge bit by pulling the sda low at the 9th clock; see figure 7-2. figure 7-2 m-bus transmission signal diagram 10 1 00011 1 0 1 00011 10 1 00011 1 0 1 00011 scl sda scl sda msb lsb msb lsb msb lsb msb lsb acknowledge bit no acknowledge start signal stop signal repeated start signal start signal stop signal acknowledge bit no acknowledge tpg 47
motorola 7-4 mc68hc05bd3 m-bus serial interface 7 7.2.3 data transfer once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a direction speci?d by the r/w bit sent by the calling master. each data byte is 8 bits long. data can be changed only when scl is low and must be held stable when scl is high as shown in figure 7-2. one clock pulse is for one bit of data transfer, msb is transferred ?st. each data byte has to be followed by an acknowledge bit. hence, one complete data byte transfer requires 9 clock pulses. if the slave receiver does not acknowledge the master, the sda line should be left high by the slave, the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. if the master receiver does not acknowledge the slave transmitter after one byte transmission, it means an ?nd of data to the slave. the slave shall release the sda line for the master to generate stop or start signal. 7.2.4 repeated start signal as shown in figure 7-2, a repeated start signal is to generate a start signal without ?st generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 7.2.5 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal ?st. this is called repeat start. a stop signal is de?ed as a low to high transition of sda while scl is at a logical high; see figure 7-2. 7.2.6 arbitration procedure this interface circuit is a true multi-master system which allows more than one master to be connected. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock. the clock low period is equal to the longest clock low period among the masters; and the clock high period is the shortest among the masters. a data arbitration procedure determines the priority. a master will lose arbitration if it transmits a logic ? while the others transmit logic ?? the losing master will immediately switch over to slave receive mode and stops its data and clock outputs. the transition from master to slave mode will not generate a stop condition. meanwhile, a software bit will be set by hardware to indicate loss of arbitration. tpg 48
mc68hc05bd3 motorola 7-5 m-bus serial interface 7 7.2.7 clock synchronization since wire-and logic is performed on the scl line, a high to low transition on scl line will affect the devices connected to the bus. the devices start counting their low period and once a device's clock has gone low, it will hold the scl line low until the clock high state is reached. however, the change of low to high in this device clock may not change the state of the scl line, if another device clock is still in its low period. therefore synchronized clock scl will be held low by the device which releases scl to a logic high in the last place. devices with shorter low periods enter a high wait state during this time (see figure 7-3). when all devices concerned have counted off their low period, the synchronized clock scl line will be released and go high. all of them will start counting their high periods. the ?st device to complete its high period will again pull the scl line low. 7.2.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave device may hold the scl low after completion of one byte transfer (9 bits). in such case, it will halt the bus clock and force the master clock in a wait state until the slave releases the scl line. 7.3 m-bus registers there are ?e registers used in the m-bus interface, these are discussed in the following paragraphs. figure 7-3 clock synchronization scl1 scl2 scl internal counter reset wait start counting high period tpg 49
motorola 7-6 mc68hc05bd3 m-bus serial interface 7 7.3.1 m-bus address register (madr) mad1-mad7 are the slave address bits of the m-bus module. 7.3.2 m-bus frequency register (mfdr) fd0-fd4 are used for clock rate selection. the serial bit clock frequency is equal to the cpu clock divided by the divider shown in table 7-1. for a 4mhz external crystal operation (2mhz internal operating frequency), the serial bit clock frequency of m-bus ranges from 460hz to 90,909hz. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $0017 mad7 mad6 mad5 mad4 mad3 mad2 mad1 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $0018 fd4 fd3 fd2 fd1 fd0 0000 0000 table 7-1 m-bus prescaler fd4 fd3 fd2 fd1 fd0 divider fd4 fd3 fd2 fd1 fd0 divider 00000 22 10000352 00001 24 10001384 00010 28 10010448 00011 34 10011544 00100 44 10100704 00101 48 10101768 00110 56 10110896 00111 68 10111 1088 01000 88 11000 1408 01001 96 11001 1536 0 1 0 1 0 112 1 1 0 1 0 1792 0 1 0 1 1 136 1 1 0 1 1 2176 0 1 1 0 0 176 1 1 1 0 0 2816 0 1 1 0 1 192 1 1 1 0 1 3072 0 1 1 1 0 224 1 1 1 1 0 3584 0 1 1 1 1 272 1 1 1 1 1 4352 tpg 50
mc68hc05bd3 motorola 7-7 m-bus serial interface 7 7.3.3 m-bus control register (mcr) register bit de?itions: men - m-bus enable 1 (set) m-bus interface system enabled. 0 (clear) m-bus interface system disabled. mien - m-bus interrupt enable 1 (set) m-bus interrupt enabled. 0 (clear) m-bus interrupt disabled. this bit enables the mif (in msr) for m-bus interrupts. msta - master/slave select 1 (set) m-bus is set for master mode operation. 0 (clear) m-bus is set for slave mode operation. upon reset, this bit is cleared. when this bit is changed from 0 to 1, a start signal is generated on the bus, and the master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operation mode changes from master to slave. in master mode, a bit clear immediately followed by a bit set of this bit generates a repeated start signal without generating a stop signal. mtx - transmit/receive mode select 1 (set) m-bus is set for transmit mode. 0 (clear) m-bus is set for receive mode. txak - acknowledge enable 1 (set) do not send acknowledge signal. 0 (clear) send acknowledge signal at 9th clock bit. if cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data. if set, no acknowledge signal response. this is an active low control bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $0019 men mien msta mtx txak 0000 0000 tpg 51
motorola 7-8 mc68hc05bd3 m-bus serial interface 7 7.3.4 m-bus status register (msr) the mif and mal bits are software clearable; while the other bits are read only. mcf - data transfer complete 1 (set) a byte transfer has been completed. 0 (clear) a byte is being transfer. when mcf is set, the mif (m-bus interrupt) bit is also set. an m-bus interrupt is generated if the mien bit is set. maas - addressed as slave 1 (set) currently addressed as a slave. 0 (clear) not currently addressed. this maas bit is set when its own speci? address (m-bus address register) matches the calling address. when maas is set, the mif (m-bus interrupt) bit is also set. an interrupt is generated if the mien bit is set. then cpu needs to check the srw bit and set its mtx bit accordingly. writing to the m-bus control register clears this bit. mbb - bus busy 1 (set) m-bus busy. 0 (clear) m-bus idle. this bit indicates the status of the bus. when a start signal is detected, mbb is set. when a stop signal is detected, it is cleared. mal - arbitration lost 1 (set) lost arbitration in master mode. 0 (clear) no arbitration lost. this arbitration lost ?g is set when the m-bus master loses arbitration during a master transmission mode. when mal is set, the mif (m-bus interrupt) bit is also set. this bit must be cleared by software. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $001a mcf maas mbb mal srw mif rxak 1000 0001 tpg 52
mc68hc05bd3 motorola 7-9 m-bus serial interface 7 srw - slave r/w select 1 (set) read from slave, from calling master 0 (clear) write to slave from calling master. when maas is set, the r/w command bit of the calling address sent from the master is latched into this srw bit. by checking this bit, the cpu can then select slave transmit/receive mode by con?uring mtx bit of the m-bus control register. mif - m-bus interrupt 1 (set) an m-bus interrupt has occurred. 0 (clear) an m-bus interrupt has not occurred. when this bit is set, an interrupt is generated to the cpu if mien is set. this bit is set when one of the following events occurs: 1) completion of one byte of data transfer. it is set at the falling edge of the 9th clock - mcf set. 2) a match of the calling address with its own speci? address in slave mode - maas set. 3) a loss of bus arbitration - mal set. this bit must be cleared by software in the interrupt routine. rxak - receive acknowledge 1 (set) no acknowledgment signal detected. 0 (clear) acknowledgment signal detected after 8 bits data transmitted. if cleared, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. if set, no acknowledge signal has been detected at the 9th clock. this is an active low status ?g. 7.3.5 m-bus data i/o register (mdr) in master transmit mode, data written into this register is sent to the bus automatically, with the most signi?ant bit out ?st. in master receive mode, reading of this register initiates receiving of the next byte data. in slave mode, the same function applies after it has been addressed. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $001b md7 md6 md5 md4 md3 md2 md1 md0 uuuu uuuu tpg 53
motorola 7-10 mc68hc05bd3 m-bus serial interface 7 figure 7-4 flowchart of m-bus interrupt routine clear mif master mode? tx/rx? arbitration last byte transmitted? last byte to be read? maas=1? clear mal lost? maas=1? srw=1? set tx mode write to mdr rti set rx mode dummy read mdr tx/rx? generate stop signal ack from receiver? last 2nd byte to read? rxak=0? write to mdr generate stop signal txak=1 write to mdr read from mdr n y rx tx n y n n y y n n y y tx rx n y y n y n y n tpg 54
mc68hc05bd3 motorola 7-11 m-bus serial interface 7 7.4 programming considerations 7.4.1 initialization reset will put the m-bus control register to its default status. before the interface can be used to transfer serial data, the following initialization procedure must be carried out. 1) update frequency divider register (mfdr) to select an scl frequency. 2) update m-bus address register (madr) to de?e its own slave address. 3) set men bit of m-bus control register (mcr) to enable the m-bus interface system. 4) modify the bits of m-bus control register (mcr) to select master/slave mode, transmit/receive mode, interrupt enable or not. 7.4.2 generation of a start signal and the first byte of data transfer after completion of the initialization procedure, serial data can be transmitted by selecting the master transmit mode. if the device is connected to a multi-master bus system, the state of the m-bus busy bit (mbb) must be tested to check if the serial bus is free. if the bus is free (mbb=0), the start condition and the ?st byte (the slave address) can be sent. an example program which generates the start signal and transmits the ?st data byte (slave address) is shown below: sei ; disable interrupt chflag brset 5,msr,chflag ; check the mbb bit of the ; status register. if it is ; set, wait until it is clear txstart bset 4,mcr ; set transmit mode bset 5,mcr ; set master mode ; i.e. generate start condition lda #calling ; get the calling address sta mdr ; transmit the calling ; address cli ; enable interrupt 7.4.3 software responses after transmission or reception of a byte upon the completion of the transmission or reception of a data byte, the data transferring bit (mcf) will be set, indicating one byte communication has been ?ished. the m-bus interrupt bit (mif) will also be set to generate an m-bus interrupt if the interrupt is enabled. software must clear the tpg 55
motorola 7-12 mc68hc05bd3 m-bus serial interface 7 mif bit in the interrupt routine ?st. the mcf bit can be cleared by reading the m-bus data i/o register (mdr) in receive mode or writing to the mdr in transmit mode. software may serve the m-bus i/o in the main program by monitoring the mif bit if the interrupt is disabled. the following is an example of a software response by a master in transmit mode in the interrupt routine (see figure 7-4). isr bclr 1,msr ; clear the mif flag brclr 5,mcr,slave ; check the msta flag, ; branch if slave mode brclr 4,mcr,receive ; check the mode flag, ; branch if in receive mode brset 0,msr,end ; check ack from receiver ; if no ack, end of ; transmission transmit lda databuf ; get the next byte of data sta mdr ; transmit the data 7.4.4 generation of the stop signal a data transfer ends with a stop signal generated by the master device. a master in transmit mode can simply generate a stop signal after all the data have been transmitted. the following is an example showing how a stop condition is generated by a master in transmit mode. mastx brset 0,msr,end ; if no ack, branch to end lda txcnt ; get value from the ; transmitting counter beq end ; if no more data, branch to ; end lda databuf ; get next byte of data sta mdr ; transmit the data dec txcnt ; decrease the txcnt bra emastx ; exit end bclr 5,mcr ; generate a stop condition emastx rti ; return from interrupt if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data. this can be achieved by setting the transmit acknowledge bit (txak) before reading the 2nd last byte of data. before reading the last byte of data, a stop signal must be generated ?st. the following is an example showing how a stop signal is generated by a master in receive mode. masr dec rxcnt beq enmasr ; last byte to be read lda rxcnt deca ; check last 2nd byte to be read bne nxmar ; not last one or last second tpg 56
mc68hc05bd3 motorola 7-13 m-bus serial interface 7 lamar bset 3,mcr ; last second, disable ack ; transmitting bra nxmar enmasr bclr 5,mcr ; last one, generate 'stop' ; signal nxmar lda mdr ; read data and store sta rxbuf rti 7.4.5 generation of a repeated start signal at the end of data transfer, if the master still wants to communicate on the bus, it can generate another start signal followed by another slave address without ?st generating a stop signal. a program example is as shown. restart bclr 5,mcr ; another start (restart) is bset 5,mcr ; generated by these two ; consecutive instructions lda #calling ; get the calling address sta mdr ; transmit the calling ; address 7.4.6 slave mode in the slave service routine, the master addressed as slave bit (maas) should be tested to check if a calling of its own address has been received (figure 7-4). if maas is set, software should set the transmit/receive mode select bit (mtx bit of mcr) according to the r/w command bit (srw). writing to the mcr clears the maas automatically. a data transfer may then be initiated by writing to mdr or a dummy read from mdr. in the slave transmit routine, the received acknowledge bit (rxak) must be tested before transmitting the next byte of data. rxak, if set indicates the end of data signal from the master receiver, the slave transmitter must then switch from transmit mode to receive mode by software and a dummy read must follow to release the scl line so that the master can generate a stop signal. 7.4.7 arbitration lost if more than one master want to acquire the bus simultaneously, only one master can win and the others will lose arbitration. the losing device immediately switches to slave receive mode by m-bus hardware. its data output to the sda line is stopped, but internal transmit clock still runs until the end of the data byte transmission. an interrupt occurs when this dummy byte transmission tpg 57
motorola 7-14 mc68hc05bd3 m-bus serial interface 7 is accomplished with mal=1 and msta=0. if one master attempts to start transmission while the bus is being controlled by another master, the transmission will be inhibited; the msta bit will be changed from 1 to 0 without generating stop condition; an interrupt will be generated and the mal bit set to indicate that the attempt to acquire the bus has failed. considering these cases, the slave service routine should test the mal bit ?st, and software should clear the mal bit if it is set. tpg 58
mc68hc05bd3 motorola 8-1 sync signal processor 8 8 sync signal processor the functions of the ssp include polarity correction, sync separation, sync pulse reshaper, sync pulse detectors, horizontal line counter, vertical frequency counter, and free running signals generator. in addition, interrupt can be generated for each vertical frame at a user speci?d horizontal line number. the processor accepts either composite or separate sync inputs. for separate sync inputs, the httl and vttl outputs are identical to the incoming horizontal sync with negative sync polarity. as for composite sync input, reassembled horizontal sync pulses can be inserted during the vertical sync period. the vttl output is triggered by the leading edge of the incoming vertical sync pulse, and the sync pulse will be widened by 9.5 m s. both hsync and vsync inputs have internal ?ter to improve noise immunity. any pulse that is shorter than an internal bus clock period, will be regarded as a glitch, and will be ignored. note: all quoted timings in this section are based on the assumption that the internal bus frequency is 2mhz, i.e. t cyc =0.5 m s. 8.1 functional blocks the architecture of the sync signal processor is shown in figure 8-1. each of the functional blocks are described in the following paragraphs. 8.1.1 polarity correction the polarity correction block of the sync signal processor accepts the input sync signals (hsync/vsync) and converts them to negative polarity signals, regardless of the polarity of the inputs. the following describes the methodologies used in polarity correction. tpg 59
motorola 8-2 mc68hc05bd3 sync signal processor 8 8.1.1.1 separate vertical sync input to test the polarity of the input sync signal, the duration of the low pulse is examined. if the low period is longer than a speci? value (512 m s or 1024t cyc ), as in the case of positive polarity input sync, the input sync will be inverted before output. for negative polarity input sync signal, it is anticipated that the duration of the low pulse would be shorter than the speci? value, and the input sync signal passes through to the output without inversion. this polarity correction is a continuous process, and the error margin is equal to the maximum permissible sync pulse width speci?d (512 m s or 1024t cyc ). at power-up or system reset, negative polarity at input is assumed. figure 8-1 sync signal processor block diagram sync detector v freq. register vsync counter vsync reshaper sync detector polarity corrector sync signal control reg. hsync counter line freq. registers interrupt circuit composite polarity corrector sync separator & insertion r r s clk gen. mux mux mux h free v free vsync hsync vttl httl hdet vdet sout vsin fout interrupt $11 $0d $0e v h $0f $10 tpg 60
mc68hc05bd3 motorola 8-3 sync signal processor 8 8.1.1.2 separate horizontal or composite sync input since the input at hsync can be either a pure horizontal sync signal or a composite sync signal, different methodologies are used in polarity correction. unlike the polarity correction for vsync, both the high pulse and low pulse of the sync signal at hsync are examined. if the pulse, either active high or low, is longer than a certain period (8 m s or 16 t cyc ), it will be regarded as a long pulse. if there are 8 consecutive low long pulses, the input sync signal will be con?med as a positive polarity sync signal, and will be inverted. if there are 8 consecutive high long pulses, it will be con?med as a negative polarity sync signal. the operation of this module is also continuous, and the error margin is equal to the period of the pre-set number (default is 8) of horizontal sync pulses. at power-up or system reset, negative polarity at input is assumed. 8.1.2 sync detection the sync detector determines whether the incoming sync signal is active. both sync high and low pulse widths must be within the speci? values to be regarded as active. hdet and vdet ?gs will be set if the hsync and vsync signals are active, respectively. figure 8-2 sync signal polarity correction negative polarity pure horizontal sync signal positive polarity pure horizontal sync signal negative polarity composite sync signal positive polarity composite sync signal tpg 61
motorola 8-4 mc68hc05bd3 sync signal processor 8 8.1.3 free-running pseudo sync signal generator if either hsync or vsync is absent, a free-running sync signal generator will be enabled. it generates a pseudo vertical sync at 63.5hz (1/(tcyc x 31488)) and a pseudo horizontal sync at either 48.8khz (1/(t cyc x 41)) or 62.5khz (1/(t cyc x 32)), depending on the status of fout. this set of free running sync signals replaces the inactive sync signals at the inputs and will be fed to the vttl and httl pins if the pins are selected for vttl and httl function. 8.1.4 sync separation figure 8-3 is a block diagram of the sync separator which includes the duration counters for the high and low pulses, a counter for the number of valid horizontal sync pulses, a register to hold the number of horizontal lines per frame, a logic block for horizontal and vertical sync pulse separation, a comparator, and a sync pulse insertion circuit. the low pulse duration counter examines the low pulse width of the incoming composite sync signal. if it is within the horizontal sync pulse limit (8 m s or 16 t cyc ), a horizontal sync pulse is detected and the horizontal sync pulse counter is advanced. if the low pulse is wider than the limit, figure 8-3 sync separator sync separation logic sync insertion circuit comparator low pulse duration counter high pulse duration counter horizontal sync register horizontal sync pulse counter clk hsync load reset count in out equal hsync vsync ?ish (after polarity correction) tpg 62
mc68hc05bd3 motorola 8-5 sync signal processor 8 a vertical sync pulse is detected, and the content of the horizontal sync pulse counter is loaded into the horizontal sync register before the low pulse duration counter is reset. comparator compares the values of the horizontal sync pulse counter and horizontal sync register, and gives the equal signal to the sync separation logic. high pulse duration counter examines the high pulse width of the incoming composite sync signal. if it is longer than a speci? value (8 m s or 16 t cyc ), the vertical sync pulse has ?ished and ?ish signal will be given to the sync separation logic. sync separation logic passes the composite sync signal to the hsync output, until there is an ?qual signal from the comparator. the hsync output will then output a reassembled waveform by the sync insertion circuit to emulate the hsync pulses, and the vsync output is set to low at the coming falling edge of the composite signal. after the ?ish signal has been sensed, the vsync output is ?ed to high, and the hsync output follows the composite sync input again. 8.1.5 vertical sync pulse reshaper for separate sync inputs, the vertical sync pulse width vttl equals to the incoming vertical sync input. for composite sync input, the sync pulse reshaper widens the vttl pulse width by 9.5 m s. 8.1.6 sync signal counters there are two counters (horizontal line counter and vertical frequency counter) to count the number of horizontal sync pulses and the number of system clock cycles between two vertical sync pulses. these two data can be read by the cpu to check the signal frequencies and can be used to determine the video mode. figure 8-4 shows a more detailed block diagram of these counters. the 13-bit vertical frequency register encompasses vertical frequency range from approximately 15hz to 125khz. figure 8-5 shows the vertical frequency counter timing. it indicates that there will be 1 count error on the reading from the register for the same vertical frequency. 8.2 vsync interrupt the sync signal processor will generate interrupts to the cpu if the vsync interrupt enable (vsie) bit is set, and the i-bit in the condition code register (ccr) is cleared. the interrupt will occur at each leading edge of vsync. the interrupt vector address is at $3ff8-$3ff9, and the interrupt latch is cleared automatically by fetching of the interrupt vectors. tpg 63
motorola 8-6 mc68hc05bd3 sync signal processor 8 figure 8-4 sync signal counters block diagram figure 8-5 vertical frequency counter timing 13-bit vertical frequency register 13-bit counter 12-bit counter 12-bit horizontal line count register negative edge detector vsync hsync system clock r $0d $0e $0f $10 ? 16 negative edge detector r ph2 vsynin counter signal reset ph2 ? 16 case1 ph2 ? 16 case2 counter resets at 4 ph2 cycles after falling edge of vsynin counter advances at the rising edge of the clock 1. the value of the counter will be loaded into the register before it is reset. 2. the vertical frequency counter is clocked by a ph2 ? 16 clock. 3. because of the asynchronous nature between ph2 and vsynin, the register will have one more count in case 2 than in case 1. tpg 64
mc68hc05bd3 motorola 8-7 sync signal processor 8 8.3 registers there are seven registers associated with the sync signal processor, these are described below. 8.3.1 sync signal control & status register (sscsr) vpol - vertical sync input polarity 1 (set) vsync input is positive polarity. 0 (clear) vsync input is negative polarity. vertical sync input polarity ?g indicates the polarity of the incoming signal at the vsync input. hpol - horizontal sync input polarity 1 (set) hsync input is positive polarity. 0 (clear) hsync input is negative polarity. horizontal sync input polarity ?g indicates the polarity of the incoming signal at the hsync input. vdet - vertical sync signal detect 1 (set) an active vertical sync is detected at vsync input. 0 (clear) no vertical sync signal at vsync input; use internal generated vsync for vttl. vertical sync signal detect ?g, if set, indicates an active input vertical sync signal has been detected. if cleared, it indicates there is no active signal, and the vttl will output the internally generated vsync signal. an active vertical sync signal is de?ed as: vdet = (vsync pulse width < 480 m s or 960t cyc )?vsync period < 65.5ms or 131x10 3 t cyc ) hdet - horizontal sync signal detect 1 (set) an active horizontal sync is detected at hsync input. 0 (clear) no horizontal sync signal at hsync input; use internal generated hsync for httl. horizontal sync signal detect ?g, if set, indicates an active input horizontal sync signal has been detected. if cleared, it indicates there is no active signal, and the httl will output the internally generated hsync signal. an active horizontal sync signal is de?ed as: hdet=(hsync pulse width < 8 m s or 16t cyc )?9 m s or 18t cyc < hsync period < 128 m s or 256t cyc ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $000c vpol hpol vdet hdet sout insrtb fout vsin 0000 0000 tpg 65
motorola 8-8 mc68hc05bd3 sync signal processor 8 sout - sync output select 1 (set) use processed vsync and hsync inputs for vttl and httl. 0 (clear) use internally generated sync signals for vttl and httl. when cleared, the outputs to vttl and httl are the internally generated signals. when set, the outputs are the processed input signals. this bit can only be set if both vdet and hdet are logic 1s, and will be cleared automatically if vdet or hdet is not logic ?? reset clears this bit. insrtb - hsync insertion bit 1 (set) no inserted pulses. hsync remains high state during the vertical sync pulse. 0 (clear) for composite sync inputs, emulated sync pulses will be inserted into the hsync signal during the vertical sync pulse. for separate sync inputs, when this hsync insertion bit is cleared, sync pulses will continue to be the hsync signal during the vertical sync pulse. for composite sync input, when this hsync insertion bit is cleared, emulated sync pulses will be inserted into the hsync signal during the vertical sync pulse. in both cases, when this bit is set, there will be no inserted pulses, and the hsync signal will be high during the vertical sync pulse. reset clears this bit. fout - internal hsync frequency select 1 (set) 63.5hz and 62.5khz for vttl and httl outputs respectively if internally generated sync signals are selected. 0 (clear) 63.5hz and 48.8khz for vttl and httl outputs respectively if internally generated sync signals are selected. this bit selects the frequency of the free running hsync signal to httl pin if sout bit is cleared. when fout is set, 63.5hz and 62.5khz signals are output to vttl and httl, respectively. when fout is cleared, 63.5hz and 48.8khz signals are output instead. reset clears this bits. vsin - vsync input source this bit selects the source of the input sync signals. reset clears this bits. 1 (set) separated sync signals through vsync and hsync inputs. 0 (clear) composite sync signal through hsync input tpg 66
mc68hc05bd3 motorola 8-9 sync signal processor 8 8.3.2 vertical frequency registers (vfrs) this 13-bit read only register pair contains information of the vertical frame frequency. an internal counter counts the number of internal clocks between two vsync pulses. the counted value will then be transferred to this register. the data corresponds to the period of one vertical frame. this register can be read to determine if the frame frequency is valid, and to determine the video mode. however, the data is not valid if vdet bit is cleared. the frame frequency is calculated by 1/(vfr 1 x 8 m s) or 1/(vfr 1 x 16t cyc ). the table below shows examples for the vertical frequency register, all vfr numbers are in hexadecimal . 8.3.3 line frequency registers (lfrs) this 12-bit read only register pair contains the number of horizontal lines in each vertical frame. an internal line counter counts the horizontal sync pulses between two vertical sync pulses. the counted value will be transferred to this register pair. hover bit will be set if the incoming horizontal sync pulses between two vertical sync pulses are more than 4096 or there is no vertical address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset vfhr $000d vf12 vf11 vf10 vf9 vf8 0000 0000 vflr $000e vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 0000 0000 table 8-1 vertical frame frequencies vfr min. freq. max. freq. vfr min. freq. max. freq. $03c0 130.07 130.34 $0823 59.98 60.04 $03c1 129.94 130.21 $0824 59.95 60.01 $03c2 129.80 130.07 $0825 59.92 59.98 $04e2 99.92 100.08 $09c4 49.98 50.02 $04e3 99.84 100.00 $09c5 49.96 50.00 $04e4 99.76 99.92 $09c6 49.94 49.98 $06f9 69.99 70.07 $1ffd 15.262 15.266 $06fa 69.95 70.03 $1ffe 15.260 15.264 $06fb 69.91 69.99 $1fff 15.258 15.262 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset lfhr $000f hover lf11 lf10 lf9 lf8 0000 0000 lflr $0010 lf7 lf6 lf5 lf4 lf3 lf2 lf1 lf0 0000 0000 tpg 67
motorola 8-10 mc68hc05bd3 sync signal processor 8 sync input. the data can be read to determine if the line frequency is valid and to determine the video mode. however, the data is not valid if hdet or vdet bit is cleared or hover bit is set. user has to determine whether the incoming signal is separate sync or composite sync. if composite sync signal is input, the actual number of horizontal lines is the value in lfr plus one; because the internal line counter that counts the horizontal sync pulses is rising-edge triggering. if the incoming signal is a composite signal, one horizontal line counting is missed. 8.3.4 sync signal control register (sscr) this is a read/write register. interrupt will be generated at the leading edge of vsync if the vsie bit is set, i bit in ccr is cleared. the vsync interrupt vectors are at $3ff8 and $3ff9, and the interrupt latch is cleared after the interrupt vectors have been fetched. vsie - vsync interrupt enable this bit enables and disables the vsync interrupt. 1 (set) vsync interrupt enabled. 0 (clear) vsync interrupt disabled. 8.3.5 horizontal sync period width register (hpwr) this 8-bit read only register contains the period of incoming horizontal sync signal. it is sampled by t cyc so the horizontal period is equal to hpwr x 0.5 m s if t cyc is at 2mhz. as the incoming horizontal sync signal is asynchronous to the system clock, the ssp is designed so that the maximum counting error of hpwr is ?. user should use the lfr to calculate the hsync frequency if very accurate frequency detection is needed. if hpwr over?ws, the hdet in sscsr will be cleared. therefore the minimum valid hsync is 256t cyc , i.e. 7.8125khz if t cyc equals to 2mhz. note: it is not guaranteed that the hpwr counting is correct for the ?st hsync period after the trailing edge of vsync. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $0011 vsie 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $001e hpwr7 hpwr6 hpwr5 hpwr4 hpwr3 hpwr2 hpwr1 hpwr0 0000 0000 tpg 68
mc68hc05bd3 motorola 8-11 sync signal processor 8 8.4 system operation the incoming signals can be either separate hsync and vsync or composite sync through hsync input. polarity correction is performed before the sync signals go any further into the system. the sync pulse detection block continuously monitors the signals to see if the signals are active. if the signals are not active, the circuit switches to output the internally generated sync signals. this will protect the circuits behind from being damaged by inactive signals. a typical monitor system operation is summarized in figure 8-6. note: user is required to check the hdet and vdet at vsin=0 ?st. if either or both are not detected, user then set vsin=1 to check hdet and vdet. it is because if the incoming signal is a valid composite signal, hdet and vdet are both read 1 even vsin=1. note: each time if vdet is not detected when vsin=1, user needs to clear vsin to check vdet. if vdet is still not detected, user then set vsin to check them again to decide what mode it is. tpg 69
motorola 8-12 mc68hc05bd3 sync signal processor 8 figure 8-6 typical monitor system operation hdet=1? n y vdet=0? no hsync set standby mode hdet=1? no vsync set off mode no vsync set suspend mode hover=1? y y n n set vsin=1 set vsin=1 n vdet=0? hdet=1? n n y vdet=0? hdet=1? n set sout=1 read registers vsin=1? clear 1st_time init vsin=0 1st_time=0? clear vsin=0 no hsync set 1st_time=1 clear vsin=0 hsync too high n y y n y y n y y a b a b separated sync set normal mode no hsync signal set standby mode composite sync set normal mode tpg 70
mc68hc05bd3 motorola 9-1 cpu core and instruction set 9 9 cpu core and instruction set this section provides a description of the cpu core registers, the instruction set and the addressing modes of the mc68hc05bd3. 9.1 registers the mcu contains ?e registers, as shown in the programming model of figure 9-1. the interrupt stacking order is shown in figure 9-2. 9.1.1 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. figure 9-1 programming model accumulator index register program counter stack pointer condition code register carry / borrow zero negative interrupt mask half carry 70 70 15 7 0 0 15 7 0 0 0 0 0 0 0 0 1 1 70 1 1 1 h i n z c 0 0 tpg 71
motorola 9-2 mc68hc05bd3 cpu core and instruction set 9 9.1.2 index register (x) the index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. the index register may also be used as a temporary storage area. 9.1.3 program counter (pc) the program counter is a 16-bit register, which contains the address of the next byte to be fetched. 9.1.4 stack pointer (sp) the stack pointer is a 16-bit register, which contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. these ten bits are appended to the six least signi?ant register bits to produce an address within the range of $00c0 to $00ff. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses ?e locations. 9.1.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the ?th bit indicates whether interrupts are masked. these bits can be individually tested by a program, and speci? actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. figure 9-2 stacking order condition code register accumulator index register program counter high program counter low 70 stack unstack decreasing memory address increasing memory address interrupt return tpg 72
mc68hc05bd3 motorola 9-3 cpu core and instruction set 9 interrupt (i) when this bit is set, all maskable interrupts are masked. if an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 9.2 instruction set the mcu has a set of 62 basic instructions. they can be grouped into ?e different types as follows: register/memory read/modify/write branch bit manipulation control the following paragraphs brie? explain each type. all the instructions within a given type are presented in individual tables. this mcu uses all the instructions available in the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. this instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is then stored in the index register and the low-order product is stored in the accumulator. a detailed definition of the mul instruction is shown in table 9-1. tpg 73
motorola 9-4 mc68hc05bd3 cpu core and instruction set 9 9.2.1 register/memory instructions most of these instructions use two operands. the ?st operand is either the accumulator or the index register. the second operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. refer to table 9-2 for a complete list of register/memory instructions. 9.2.2 branch instructions these instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. branch instructions are two-byte instructions. refer to table 9-3. 9.2.3 bit manipulation instructions the mcu can set or clear any writable bit that resides in the ?st 256 bytes of the memory space (page 0). all port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip ram reside in page 0. an additional feature allows the software to test and branch on the state of any bit within these locations. the bit set, bit clear, bit test and branch functions are all implemented with single instructions. for the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. refer to table 9-4. 9.2.4 read/modify/write instructions these instructions read a memory location or a register, modify or test its contents, and write the modi?d value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. refer to table 9-5 for a complete list of read/modify/write instructions. 9.2.5 control instructions these instructions are register reference instructions and are used to control processor operation during program execution. refer to table 9-6 for a complete list of control instructions. 9.2.6 tables tables for all the instruction types listed above follow. in addition there is a complete alphabetical listing of all the instructions (see table 9-7), and an opcode map for the instruction set of the m68hc05 mcu family (see table 9-8). tpg 74
mc68hc05bd3 motorola 9-5 cpu core and instruction set 9 table 9-1 mul instruction operation x:a ? x*a description multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. condition codes h : cleared i : not affected n : not affected z : not affected c : cleared source mul form addressing mode cycles bytes opcode inherent 11 1 $42 table 9-2 register/memory instructions addressing modes immediate direct extended indexed (no offset) indexed (8-bit offset) indexed (16-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles load a from memory lda a6 2 2 b6 2 3 c6 3 4 f6 1 3 e6 2 4 d6 3 5 load x from memory ldx ae 2 2 be 2 3 ce 3 4 fe 1 3 ee 2 4 de 3 5 store a in memory sta b7 2 4 c7 3 5 f7 1 4 e7 2 5 d7 3 6 store x in memory stx bf 2 4 cf 3 5 ff 1 4 ef 2 5 df 3 6 add memory to a add ab 2 2 bb 2 3 cb 3 4 fb 1 3 eb 2 4 db 3 5 add memory and carry to a adc a9 2 2 b9 2 3 c9 3 4 f9 1 3 e9 2 4 d9 3 5 subtract memory sub a0 2 2 b0 2 3 c0 3 4 f0 1 3 e0 2 4 d0 3 5 subtract memory from a with borrow sbc a2 2 2 b2 2 3 c2 3 4 f2 1 3 e2 2 4 d2 3 5 and memory with a and a4 2 2 b4 2 3 c4 3 4 f4 1 3 e4 2 4 d4 3 5 or memory with a ora aa 2 2 ba 2 3 ca 3 4 fa 1 3 ea 2 4 da 3 5 exclusive or memory with a eor a8 2 2 b8 2 3 c8 3 4 f8 1 3 e8 2 4 d8 3 5 arithmetic compare a with memory cmp a1 2 2 b1 2 3 c1 3 4 f1 1 3 e1 2 4 d1 3 5 arithmetic compare x with memory cpx a3 2 2 b3 2 3 c3 3 4 f3 1 3 e3 2 4 d3 3 5 bit test memory with a (logical compare) bit a5 2 2 b5 2 3 c5 3 4 f5 1 3 e5 2 4 d5 3 5 jump unconditional jmp bc 2 2 cc 3 3 fc 1 2 ec 2 3 dc 3 4 jump to subroutine jsr bd 2 5 cd 3 6 fd 1 5 ed 2 6 dd 3 7 tpg 75
motorola 9-6 mc68hc05bd3 cpu core and instruction set 9 table 9-3 branch instructions relative addressing mode function mnemonic opcode # bytes # cycles branch always bra 20 2 3 branch never brn 21 2 3 branch if higher bhi 22 2 3 branch if lower or same bls 23 2 3 branch if carry clear bcc 24 2 3 (branch if higher or same) (bhs) 24 2 3 branch if carry set bcs 25 2 3 (branch if lower) (blo) 25 2 3 branch if not equal bne 26 2 3 branch if equal beq 27 2 3 branch if half carry clear bhcc 28 2 3 branch if half carry set bhcs 29 2 3 branch if plus bpl 2a 2 3 branch if minus bmi 2b 2 3 branch if interrupt mask bit is clear bmc 2c 2 3 branch if interrupt mask bit is set bms 2d 2 3 branch if interrupt line is low bil 2e 2 3 branch if interrupt line is high bih 2f 2 3 branch to subroutine bsr ad 2 6 table 9-4 bit manipulation instructions addressing modes bit set/clear bit test and branch function mnemonic opcode # bytes # cycles opcode # bytes # cycles branch if bit n is set brset n (n=0?) 2? 3 5 branch if bit n is clear brclr n (n=0?) 01+2? 3 5 set bit n bset n (n=0?) 10+2? 2 5 clear bit n bclr n (n=0?) 11+2? 2 5 tpg 76
mc68hc05bd3 motorola 9-7 cpu core and instruction set 9 table 9-5 read/modify/write instructions addressing modes inherent (a) inherent (x) direct indexed (no offset) indexed (8-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles increment inc 4c 1 3 5c 1 3 3c 2 5 7c 1 5 6c 2 6 decrement dec 4a 1 3 5a 1 3 3a 2 5 7a 1 5 6a 2 6 clear clr 4f 1 3 5f 1 3 3f 2 5 7f 1 5 6f 2 6 complement com 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 negate (twos complement) neg 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 rotate left through carry rol 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 rotate right through carry ror 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 logical shift left lsl 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 logical shift right lsr 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 arithmetic shift right asr 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 test for negative or zero tst 4d 1 3 5d 1 3 3d 2 4 7d 1 4 6d 2 5 multiply mul 42 1 11 table 9-6 control instructions inherent addressing mode function mnemonic opcode # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 10 return from subroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 stop stop 8e 1 2 wait wait 8f 1 2 tpg 77
motorola 9-8 mc68hc05bd3 cpu core and instruction set 9 table 9-7 instruction set mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c adc add and asl asr bcc bclr bcs beq bhcc bhcs bhi bhs bih bil bit blo bls bmc bmi bms bne bpl bra brn brclr brset bset bsr clc 0 cli 0 clr 01 cmp condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 78
mc68hc05bd3 motorola 9-9 cpu core and instruction set 9 com 1 cpx dec eor inc jmp jsr lda ldx lsl lsr 0 mul 00 neg nop ora rol ror rsp rti ????? rts sbc sec 1 sei 1 sta stop 0 stx sub swi 1 tax tst txa wait 0 table 9-7 instruction set (continued) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 79
motorola 9-10 mc68hc05bd3 cpu core and instruction set 9 table 9-8 m68hc05 opcode map bit manipulation branch read/modify/write control register/memory btb bsc rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix high 0123456789abcdef high low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 low 0 0000 553533659 234543 0 0000 brset0 bset0 bra neg nega negx neg neg rti sub sub sub sub sub sub 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 1 0001 553 6 234543 1 0001 brclr0 bclr0 brn rts cmp cmp cmp cmp cmp cmp 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 2 0010 553 11 234543 2 0010 brset1 bset1 bhi mul sbc sbc sbc sbc sbc sbc 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 3 0011 5535336510 234543 3 0011 brclr1 bclr1 bls com coma comx com com swi cpx cpx cpx cpx cpx cpx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 4 0100 55353365 234543 4 0100 brset2 bset2 bcc lsr lsra lsrx lsr lsr and and and and and and 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 0101 553 234543 5 0101 brclr2 bclr2 bcs bit bit bit bit bit bit 3 btb 2 bsc 2 rel 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 6 0110 55353365 234543 6 0110 brset3 bset3 bne ror rora rorx ror ror lda lda lda lda lda lda 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 7 0111 55353365 2 45654 7 0111 brclr3 bclr3 beq asr asra asrx asr asr tax sta sta sta sta sta 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix 8 1000 55353365 2234543 8 1000 brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eor eor eor eor eor 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 9 1001 55353365 2234543 9 1001 brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix a 1010 55353365 2234543 a 1010 brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix b 1011 553 2234543 b 1011 brclr5 bclr5 bmi sei add add add add add add 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix c 1100 55353365 2 23432 c 1100 brset6 bset6 bmc inc inca incx inc inc rsp jmp jmp jmp jmp jmp 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix d 1101 55343354 2656765 d 1101 brclr6 bclr6 bms tst tsta tstx tst tst nop bsr jsr jsr jsr jsr jsr 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 rel 2 dir 3 ext 3 ix2 2 ix1 1 ix e 1110 553 2 234543 e 1110 brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 5535336522 45654 f 1111 brclr7 bclr7 bih clr clra clrx clr clr wait txa stx stx stx stx stx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 3 0 0000 sub 1ix opcode in hexadecimal opcode in binary address mode cycles bytes mnemonic legend abbreviations for address modes and registers bsc btb dir ext inh imm ix ix1 ix2 rel a x bit set/clear bit test and branch direct extended inherent immediate indexed (no offset) indexed, 1 byte (8-bit) offset indexed, 2 byte (16-bit) offset relative accumulator index register not implemented tpg 80
mc68hc05bd3 motorola 9-11 cpu core and instruction set 9 9.3 addressing modes ten different addressing modes provide programmers with the ?xibility to optimize their code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. short absolute (direct) and long absolute (extended) addressing are also included. one or two byte direct addressing instructions access all data bytes in most applications. extended addressing permits jump instructions to reach all memory locations. the term ?ffective address (ea) is used in describing the various addressing modes. the effective address is de?ed as the address from which the argument for an instruction is fetched or stored. the ten addressing modes of the processor are described below. parentheses are used to indicate ?ontents of the location or register referred to. for example, (pc) indicates the contents of the location pointed to by the pc (program counter). an arrow indicates ?s replaced by and a colon indicates concatenation of two bytes. for additional details and graphical illustrations, refer to the m6805 hmos/m146805 cmos family microcomputer/ microprocessor user's manual or to the m68hc05 applications guide . 9.3.1 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. these instructions are one byte long. 9.3.2 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). ea = pc+1; pc ? pc+2 9.3.3 direct in the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) tpg 81
motorola 9-12 mc68hc05bd3 cpu core and instruction set 9 9.3.4 extended in the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. when using the motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically selects the short form of the instruction. ea = (pc+1):(pc+2); pc ? pc+3 address bus high ? (pc+1); address bus low ? (pc+2) 9.3.5 indexed, no offset in the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. this addressing mode can access the ?st 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. ea = x; pc ? pc+1 address bus high ? 0; address bus low ? x 9.3.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. therefore the operand can be located anywhere within the lowest 511 memory locations. this addressing mode is useful for selecting the mth element in an n element table. ea = x+(pc+1); pc ? pc+2 address bus high ? k; address bus low ? x+(pc+1) where k = the carry from the addition of x and (pc+1) 9.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. this address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. ea = x+[(pc+1):(pc+2)]; pc ? pc+3 address bus high ? (pc+1)+k; address bus low ? x+(pc+2) where k = the carry from the addition of x and (pc+2) tpg 82
mc68hc05bd3 motorola 9-13 cpu core and instruction set 9 9.3.8 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the pc if, and only if, the branch conditions are true. otherwise, control proceeds to the next instruction. the span of relative addressing is from ?26 to +129 from the opcode address. the programmer need not calculate the offset when using the motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. ea = pc+2+(pc+1); pc ? ea if branch taken; otherwise ea = pc ? pc+2 9.3.9 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. the byte following the opcode speci?s the address of the byte in which the speci?d bit is to be set or cleared. any read/write bit in the ?st 256 locations of memory, including i/o, can be selectively set or cleared with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) 9.3.10 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit to be tested and its condition (set or clear) is included in the opcode. the address of the byte to be tested is in the single byte immediately following the opcode byte (ea1). the signed relative 8-bit offset in the third byte (ea2) is added to the pc if the speci?d bit is set or cleared in the speci?d memory location. this single three-byte instruction allows the program to branch based on the condition of any readable bit in the ?st 256 locations of memory. the span of branch is from ?25 to +130 from the opcode address. the state of the tested bit is also transferred to the carry bit of the condition code register. ea1 = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) ea2 = pc+3+(pc+2); pc ? ea2 if branch taken; otherwise pc ? pc+3 tpg 83
motorola 9-14 mc68hc05bd3 cpu core and instruction set 9 this page left blank intentionally tpg 84
mc68hc05bd3 motorola 10-1 low power modes 10 10 low power modes the mc68hc05bd3 has only one low-power operating mode?he wait mode. the wait instruction provides the only mode that reduces the power required for the mcu by stopping cpu internal clock. the stop instruction is not implemented in its normal sense. the stop instruction will be interpreted as the nop instruction by the cpu if it is ever encountered. the ?w of the wait mode is shown in figure 10-1. 10.1 stop mode stop mode is not implemented on the mc68hc05bd3. the stop instruction will be treated and executed as a nop instruction. therefore, the i-bit in the condition code register will not be cleared. 10.2 wait mode in the wait mode the internal processor clock is halted, suspending all processor and internal bus activities. other internal clocks remain active, permitting interrupts to be generated from the multi-function timer, m-bus interface, and the sync signal processor, or a reset to be generated from the cop watchdog timer. the timer may be used to generate a periodic exit from the wait mode. execution of the wait instruction automatically clears the i-bit in the condition code register, so that any hardware interrupt can wake up the mcu. all other registers, memory, and input/output lines remain in their previous states. tpg 85
motorola 10-2 mc68hc05bd3 low power modes 10 10.3 cop watchdog timer considerations the cop watchdog timer is always enabled in mc68hc05bd3. it will reset the mcu when it times out. for a system that must have intentional uses of the wait mode, care must be taken to prevent such situations from happening during normal operations by arranging timely interrupts to reset the cop watchdog timer. figure 10-1 wait flowchart y external n wait external oscillator active and internal timer clock active stop internal processor clock, clear i bit in ccr reset? internal cop reset? external h/w reset? internal interrupt? restart internal processor clock 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine n n n y y y tpg 86
mc68hc05bd3 motorola 11-1 operating modes 11 11 operating modes the mc68hc05bd3/mc68hc05bd5/ mc68hc705bd3 mcu has two modes of operation, the user mode and the self-check/ bootstrap mode. figure 11-1 shows the ?wchart of entry to these two modes, and table 11-1 shows operating mode selection. figure 11-1 flowchart of mode entering pb5 = v dd ? reset irq self-check/ mode user mode 5v 9v ? n y y (normal mode) bootstrap self-check mode is for mc68hc05bd3/bd5 bootstrap mode is for mc68hc705bd3 note: tpg 87
motorola 11-2 mc68hc05bd3 operating modes 11 11.1 user mode (normal operation) the normal operating mode of the mc68hc05bd3/mc68hc05bd5/ mc68hc705bd3 is the user mode. the user mode will be entered if the reset line is brought low, and the irq pin is within its normal operational range (v ss to v dd ), the rising edge of the reset will cause the mcu to enter the user mode. 11.2 self-check mode the self-check mode is provided on the mc68hc05bd3 and mc68hc05bd5 for the user to check device functions with an on-chip self-check program masked at location $3f00 to $3fdf under minimum hardware support. the hardware is shown in figure 11-3. figure 11-2 is the criteria to enter self-check mode, where pb5s condition is latched within ?st two clock cycles after the rising edge of the reset. pb5 can then be used for other purposes. after entering the self-check mode, cpu branches to the self-check program and carries out the self-check. self-check is a repetitive test, i.e. if all parts are checked to be good, the cpu will repeat the self-check again. therefore, the leds attached to port b will be ?shing if the device is good; else the combination of leds on-off pattern can show what part of the device is suspected to be bad. table 11-2 lists the leds on-off patterns and their corresponding indications. table 11-1 mode selection reset irq pb5 mode v ss to v dd v ss to v dd user +9v rising edge* v dd self-check/ bootstrap * minimum hold time should be 2 clock cycles, after that it can be used as a normal irq function pin. figure 11-2 self-check mode timing 5v 5v 9v pb5 irq reset +5v +5v +9v tpg 88
mc68hc05bd3 motorola 11-3 operating modes 11 figure 11-3 mc68hc05bd3 self-test circuit mc68hc05bd3 +5v 1k 1k reset irq +5v vss 1k pc0/pwm8 pc1/pwm9 pc2/pwm10 pc3/pwm11 pc4/pwm12 pc5/pwm13 pc6/pwm14/vttl pc7/pwm15/httl pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 pb0 pb1 pb2 pb3 pb4 vdd vsync hsync 8 x 4k7 d1 d2 d3 pd0/sda pd1/scl + 47 m 0.1 m +5v pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb5 2.2 m 10k + reset +5v 1n4148 20p 4mhz 20p +9v 10k 10k 2n3904 10k 3 x 4k7 8 x 100 xtal extal +5v tpg 89
motorola 11-4 mc68hc05bd3 operating modes 11 11.3 bootstrap mode the bootstrap mode is provided in the eprom part (mc68hc705bd3) as a mean of self-programming its eprom with minimal circuitry. it is entered on the rising edge of reset if irq pin is at 1.8v dd and pb5 is at logic one. reset must be held low for 4064 cycles after por (power-on reset) or for a time t rl for any other reset. the user eprom consists of 7.75k-bytes, from location $2000 to $3eff. refer to section 15 for further details on mc68hc705bd3. table 11-2 self-check report pb3 pb1 pb0 remarks flashing o.k. (self-check is on-going) 1 1 0 bad i/o 1 0 1 bad ram 1 0 0 bad rom 0 1 1 bad irq 1=led off, 0=led on tpg 90
mc68hc05bd3 motorola 12-1 electrical specifications 12 12 electrical specifications this section contains the electrical speci?ations for mc68hc05bd3. 12.1 maximum ratings this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit. for proper operation it is recommended that vin and vout be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either v ss or v dd ). 12.2 thermal characteristics (voltages referenced to v ss ) ratings symbol value unit supply voltage v dd ?.3 to +7.0 v input voltage v in v ss ?.3 to v dd +0.3 v irq v in v ss ?.3 to 2xv dd +0.3 v current drain per pin excluding v dd and v ss i d 25 ma operating temperature t a 0 to 70 c storage temperature range t stg ?5 to +150 c characteristics symbol value unit thermal resistance - plastic 40-pin dip package - plastic 42-pin sdip package q ja q ja 60 60 c/w c/w tpg 91
motorola 12-2 mc68hc05bd3 electrical specifications 12 12.3 dc electrical characteristics table 12-1 dc electrical characteristics for mc68hc05bd3 (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum typical maximum unit output voltage i load = ?0 m a i load = +10 m a v oh v ol v dd -0.1 0.1 v v output high voltage (i load =?ma) pa0-pa7, pb0-pb1, pc6-pc7, pd0-pd1 v oh v dd -0.8 v output low voltage (i load =+5ma) pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, pwm0-pwm7 v ol 0.4 v input high voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, irq , reset , extal vsync, hsync (ttl level) v ih 0.7xv dd 2.0 v dd v dd v input low voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, irq , reset , extal vsync, hsync (ttl level) v il v ss v ss 0.2xv dd 0.8 v supply current: run wait i dd 4.5 0.73 20 8 ma ma i/o ports high-z leakage current pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, pwm0-pwm7 i il 10 m a input current irq , rese t , extal, vsync, hsync i in 1 m a capacitance ports (as input or output), reset , irq , extal, xtal, hsync, vsync c out c in 12 8 pf pf notes: (1) all values shown re?ct average measurements. (2) typical values at midpoint of voltage range, 25 c only. (3) wait i dd : only timer system and ssp is active. (4) run (operating) i dd , wait i dd : measured using external square wave clock source to extal (f osc =4.2mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l =20pf on extal. (5) wait i dd : all ports con?ured as inputs, v il =0.2 vdc, v ih =v dd ?0.2 vdc. (6) wait i dd is affected linearly by the extal capacitance. tpg 92
mc68hc05bd3 motorola 12-3 electrical specifications 12 12.4 control timing table 12-2 control timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum maximum unit frequency of operation crystal option external clock option f osc dc 4.2 4.2 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc 2.1 2.1 mhz mhz processor cycle time t cyc 480 ns crystal oscillator start-up time t oxov 100 ms external reset pulse width t rl 1.5 t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 114688 917504 t cyc interrupt pulse width (edge-triggered) t ilih 125 ns interrupt pulse period t ilil (1) ? cyc extal pulse width t oh , t ol 100 t cyc notes: (1) the minimum period t ilil should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 t cyc . tpg 93
motorola 12-4 mc68hc05bd3 electrical specifications 12 12.5 m-bus timing table 12-3 m-bus interface input signal timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) parameter symbol minimum maximum unit start condition hold time t hd.sta 2t cyc clock low period t low 4.7 t cyc clock high period t high 4t cyc data set-up time t su.dat 250 ns data hold time t hd.dat 0t cyc start condition set-up time (for repeated start condition only) t su.sta 2t cyc stop condition set-up time t su.sto 2t cyc table 12-4 m-bus interface output signal timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) parameter symbol minimum maximum unit start condition hold time t hd.sta 8t cyc clock low period t low 11 t cyc clock high period t high 11 t cyc sda/scl rise time (see note 1) t r ? m s sda/scl fall time (see note 1) t f 300 ns data set-up time t su.dat t low ?t cyc ?s data hold time t hd.dat 1t cyc start condition set-up time (for repeated start condition only) t su.sta 10 t cyc stop condition set-up time t su.sto 10 t cyc note: 1. with 200pf loading on the sda/scl pins figure 12-1 m-bus timing sda scl t high t hd.sta t low t su.dat t hd.dat t su.sta t su.sto t r t f tpg 94
mc68hc05bd3 motorola 12-5 electrical specifications 12 12.6 sync signal processor timing table 12-5 sync signal processor timing (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) parameter symbol minimum maximum unit vsync input sync pulse t vi.sp 1t cyc hsync input sync pulse (except for composite sync input) t hi.sp 1t cyc vttl output sync pulse width for separate sync input t vo.sp same as input vttl output sync pulse width for composite sync input t vo.co input + 9.5 m s input + 10 m s httl output sync pulse width t ho same as input free-running vttl output sync pulse (sout clear) t fvo.sp 128 t cyc free-running vttl output period (sout clear) t fvo 31488 t cyc free-running httl output sync pulse (sout clear) t fho.sp 4t cyc free-running httl output period (sout clear) t fho 41/32 t cyc inserted httl sync pulse (insrt cleared) t ihi.sp 4t cyc inserted httl period error (insrt cleared) t ihi.er ?t cyc vsync to vttl delay (8pf loading) t vdd 30 40 ns hsync to httl delay (8pf loading) t hhd 30 40 ns hsync to vttl delay (composite sync) t hvd 30 40 ns tpg 95
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mc68hc05bd3 motorola 13-1 mechanical specifications 13 13 mechanical specifications this section provides the mechanical dimension for the 42-pin sdip and 40-pin dip packages for the mc68hc05bd3. 13.1 42-pin sdip package (case 858-01) 13.2 40-pin dip package (case 711-03)

-b- -a- c d 42 pl f k g n j 42 pl m
h l
! ! ! ! %
! ! ! #
! " $" 121 42 22 -t-

! ! ! #! %% ! $" ! ! ! ! ! ! ! ! # ! " 120 40 21 b a c n k m j l hgfd tpg 97
motorola 13-2 mc68hc05bd3 mechanical specifications 13 this page left blank intentionally tpg 98
mc68hc05bd3 motorola 14-1 mc68hc705bd3 14 14 mc68hc705bd3 the mc68hc705bd3 is functionally equivalent to mc68hc05bd3, but with increased ram size to 256 bytes and the user rom is replaced by an 7.75k-bytes user eprom (located from $2000 to $3eff). the entire mc68hc05bd3 data sheet applies to the mc68hc705bd3, with exceptions outlined in the section. 14.1 features functionally equivalent to mc68hc05bd3 256 bytes on-chip ram 7.75k-bytes user eprom 14.2 memory map figure 14-1 shows the memory map for the mc68hc705bd3. 14.3 eprom programming the following programming boards are available from motorola for programming the on-chip eprom in the mc68hc705bd3. table 14-1 mc68hc705bd3 programming boards platform board adapter for programming a single device at a time: m68hc705upgmr + m68upa05bd3p40 for 40-pin pdip for programming up to 10 devices at a time: m68hc705ugang m68upa05bd3b42 for 42-pin sdip tpg 99
motorola 14-2 mc68hc05bd3 mc68hc705bd3 14 unused port a data register $00 port b data register $01 port c data register $02 port d data register $03 port a data direction register $04 port b data direction register $05 port c data direction register $06 port d data direction register $07 mft control and status register $08 mft timer counter register $09 con?uration register 1 $0a con?uration register 2 $0b $0c $0d $0e $0f $10 $11 unused $12 unused $13 unused $14 unused $15 unused $16 mbus address register $17 mbus frequency divider register $18 mbus control register $19 mbus status register $1a mbus data register $1b $1c programming control register $1d hsync period width register $1e reserved $1f ssp control and status register vertical frequency high register vertical frequency low register line frequency high register line frequency low register sync signal control register reserved $3ff0 reserved $3ff2 mft $3ff4 mbus $3ff6 ssp $3ff8 irq $3ffa swi $3ffc reset $3ffe $20 $21 pwm2 $22 pwm3 $23 pwm4 $24 pwm5 $25 pwm6 $26 pwm7 $27 pwm8 $28 pwm9 $29 pwm10 $2a pwm11 $2b pwm12 $2c pwm13 $2d pwm14 $2e pwm15 $2f pwm0 pwm1 unused $0000 i/o 48 bytes bootstrap 16 bytes user vectors 16 bytes vectors unused user ram 256 bytes unused user eprom 7936 bytes stack 64 bytes $002f $0080 $0180 $1fff $2000 $3f00 $3fdf $3fe0 $3fef $3ff0 $3fff $3eff mc68hc705bd3 $00ff $00c0 $0030 $007f $017f bootstrap rom 480 bytes unused $1fe0 $1fdf $1e00 $1dff tpg 100
mc68hc05bd3 motorola 14-3 mc68hc705bd3 14 14.3.1 programming control register (pcr) the eprom programming control register controls the actual programming of the eprom in the mc68hc705bd3. elat - eprom latch control 1 (set) eprom address and data bus con?ured for programming (writes to eprom cause address data to be latched). eprom is in programming mode and cannot be read if elat is 1. this bit is not able be set when no v pp voltage is applied to the v pp pin. 0 (clear) eprom address and data bus con?ured for normal reads. pgm - eprom program command 1 (set) programming power switched on to eprom array. if elat 1 1 then pgm=0. 0 (clear) programming power switched off to eprom array. 14.3.2 eprom programming sequence programming the eprom of the mc68hc705bd3 is as follows: 1) set the elat bit. 2) write the data to be programmed to the address to be programmed. 3) set the pgm bit. 4) delay for the appropriate amount of time. 5) clear the pgm and the elat bits. the last action may be carried out in a single cpu write operation. it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but should be equal to v dd during normal operation. example shows address $2000 is programmed with $00. clr pcr ;reset pcr ldx #$00 ;load index register with 00 bset 1,pcr ;set elat bit lda #$00 ;load data=00 in to a sta $2000,x ;latch data and address address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $001d elat pgm ---- --00 tpg 101
motorola 14-4 mc68hc05bd3 mc68hc705bd3 14 bset 0,pcr ;program jsr delay ;call delay subroutine clr pcr ;reset pcr 14.4 dc electrical characteristics table 14-2 dc electrical characteristics for mc68hc705bd3 (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum typical maximum unit output voltage i load = ?0 m a i load = +10 m a v oh v ol v dd -0.1 0.1 v v output high voltage (i load =?ma) pa0-pa7, pb0-pb1, pc6-pc7, pd0-pd1 v oh v dd -0.8 v output low voltage (i load =+5ma) pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, pwm0-pwm7 v ol 0.4 v input high voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, irq , reset , extal vsync, hsync (ttl level) v ih 0.7xv dd 2.0 v dd v dd v input low voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, irq , reset , extal vsync, hsync (ttl level) v il v ss v ss 0.2xv dd 0.8 v supply current: run wait i dd 6 2 20 8 ma ma i/o ports high-z leakage current pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, pwm0-pwm7 i il 10 m a input current irq , rese t , extal, vsync, hsync i in 1 m a capacitance ports (as input or output), reset , irq , extal, xtal, hsync, vsync c out c in 12 8 pf pf notes: (1) all values shown re?ct average measurements. (2) typical values at midpoint of voltage range, 25 c only. (3) wait i dd : only timer system and ssp is active. (4) run (operating) i dd , wait i dd : measured using external square wave clock source to extal (f osc =4.2mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l =20pf on extal. (5) wait i dd : all ports con?ured as inputs, v il =0.2 vdc, v ih =v dd ?0.2 vdc. (6) wait i dd is affected linearly by the extal capacitance. tpg 102
mc68hc05bd3 motorola 15-1 mc68hc05bd5 15 15 mc68hc05bd5 the mc68hc05bd5 is functionally equivalent to mc68hc05bd3, but with increased ram size of 256 bytes and rom size of 7.75k-bytes. the entire mc68hc05bd3 data sheet applies to the mc68hc05bd5, with exceptions outlined in the section. 15.1 features functionally equivalent to mc68hc05bd3 256 bytes on-chip ram 7.75k-bytes user rom 15.2 memory map figure 15-1 shows the memory map for the mc68hc05bd5. tpg 103
motorola 15-2 mc68hc05bd3 mc68hc05bd5 15 unused port a data register $00 port b data register $01 port c data register $02 port d data register $03 port a data direction register $04 port b data direction register $05 port c data direction register $06 port d data direction register $07 mft control and status register $08 mft timer counter register $09 con?uration register 1 $0a con?uration register 2 $0b $0c $0d $0e $0f $10 $11 unused $12 unused $13 unused $14 unused $15 unused $16 mbus address register $17 mbus frequency divider register $18 mbus control register $19 mbus status register $1a mbus data register $1b $1c reserved $1d hsync period width register $1e reserved $1f ssp control and status register vertical frequency high register vertical frequency low register line frequency high register line frequency low register sync signal control register reserved $3ff0 reserved $3ff2 mft $3ff4 mbus $3ff6 ssp $3ff8 irq $3ffa swi $3ffc reset $3ffe $20 $21 pwm2 $22 pwm3 $23 pwm4 $24 pwm5 $25 pwm6 $26 pwm7 $27 pwm8 $28 pwm9 $29 pwm10 $2a pwm11 $2b pwm12 $2c pwm13 $2d pwm14 $2e pwm15 $2f pwm0 pwm1 self-check 224 bytes program $0000 i/o 48 bytes self-check 16 bytes user vectors 16 bytes vectors unused user ram 256 bytes unused user rom 7936 bytes stack 64 bytes $002f $0080 $0180 $1fff $2000 $3f00 $3fdf $3fe0 $3fef $3ff0 $3fff $3eff mc68hc05bd5 $00ff $00c0 $0030 $007f $017f tpg 104
mc68hc05bd3 motorola 15-3 mc68hc05bd5 15 15.3 dc electrical characteristics table 15-1 dc electrical characteristics for mc68hc05bd5 (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum typical maximum unit output voltage i load = ?0 m a i load = +10 m a v oh v ol v dd -0.1 0.1 v v output high voltage (i load =?ma) pa0-pa7, pb0-pb1, pc6-pc7, pd0-pd1 v oh v dd -0.8 v output low voltage (i load =+5ma) pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, pwm0-pwm7 v ol 0.4 v input high voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, irq , reset , extal vsync, hsync (ttl level) v ih 0.7xv dd 2.0 v dd v dd v input low voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, irq , reset , extal vsync, hsync (ttl level) v il v ss v ss 0.2xv dd 0.8 v supply current: run wait i dd 7 1.3 20 8 ma ma i/o ports high-z leakage current pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, pwm0-pwm7 i il 10 m a input current irq , rese t , extal, vsync, hsync i in 1 m a capacitance ports (as input or output), reset , irq , extal, xtal, hsync, vsync c out c in 12 8 pf pf notes: (1) all values shown re?ct average measurements. (2) typical values at midpoint of voltage range, 25 c only. (3) wait i dd : only timer system and ssp is active. (4) run (operating) i dd , wait i dd : measured using external square wave clock source to extal (f osc =4.2mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l =20pf on extal. (5) wait i dd : all ports con?ured as inputs, v il =0.2 vdc, v ih =v dd ?0.2 vdc. (6) wait i dd is affected linearly by the extal capacitance. tpg 105
motorola 15-4 mc68hc05bd3 mc68hc05bd5 15 this page left blank intentionally tpg 106
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tpg 107 general description pin description and i/o ports memory and registers resets and interrupts multi-function timer pulse width modulation m-bus serial interface sync signal processor cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705bd3 mc68hc05bd5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 general description pin description and i/o ports memory and registers resets and interrupts multi-function timer pulse width modulation m-bus serial interface sync signal processor cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705bd3 mc68hc05bd5 tpg 108
2 1 3 4 5 6 7 8 9 10 11 12 13 14 15
2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 !motorola mc68hc05bd3d/h how to reach us: mfax: rmfax0@email.sps.mot.com ?touchtone (602) 244-6609 internet: http://design-net.com usa/europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 1-800-441-2447 japan: nippon motorola ltd.; tatsumi-spd-jldc, toshikatsu otsuki, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 03-3521-8315 hong kong: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298

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